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Dive into the research topics where Edward John Coyne is active.

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Featured researches published by Edward John Coyne.


Journal of Micromechanics and Microengineering | 2010

Fabrication of silicon-blazed phase diffractive gratings using grey scale gallium implantation with KOH anisotropic etch

Edward John Coyne; Gerard M. O'Connor

The development of a two-step process for fabricating blazed diffractive gratings, with consistent efficiencies greater than 70%, using a combination of focused ion beams (FIB) for grey scale gallium mask implantation, followed by a potassium hydroxide (KOH) anisotropic wet etch is described. The target wavelength range for the diffractive optics is designed for the infra-red (IR) spectrum from 1 µm to 10 µm. The optical substrate is made from p-type (1015 cm−3) wafer grade silicon (1 0 0). Computer-generated holography is used to determine the implant pattern. This pattern is then translated into FIB script files for spatial implant dose commands. Process optimization is achieved using the implant dose range of 1 pC µm−2 to 25 pC µm−2, using a 1000 pA ion beam current with a focal diameter of 140 nm. The etch process uses a 30% KOH solution at a fixed temperature of 78 °C to achieve an etch rate of approximately 1 µm min for greatest control and repeatability. Measurements confirm that etch times ranging over 1 to 4 min achieve the required phase heights of 1–3.8 µm for the target wavelength range. Therefore, the wet etch process offers the advantages of higher throughput time with greater etch selectivity for larger phase heights when compared with photolithographic techniques. However, experimentation with diffraction gratings and circular lens patterns confirms that repeatability and control are limited to designs that have surfaces with the minimum number of convex corners due to the enhanced etching of the crystalline planes {4 1 1} relative to the {1 0 0} planes. Fabrication of diffraction grating structures on the (1 0 0) silicon wafer for the wavelengths of 1 µm and 10.6 µm confirms optical functionality with binary diffraction structures and a measured diffraction efficiency of 76% for the blazed phase profile.


international conference on microelectronic test structures | 2017

Test structure configurations for analysis of field effect influenced self-heating and thermal coupling in High Voltage SiGe HBTs

Breandan O hAnnaidh; Edward John Coyne; Bill Lane

this paper presents several test structure configurations that facilitate a comprehensive assessment of self-heating and thermal coupling effects in High Voltage SiGe HBTs in a DTI on SOI process. Several layout test structures are investigated including variations in device separations, multi-device arrays and the influence of the substrate contact in the regions outside the trench isolation, and indeed the potential for trench field effects themselves, the latter two both due to the high voltages involved. The findings are reported with a view to focus on a Compact Modelling solution implementable in a commercial CAD tool.


IEEE Transactions on Electron Devices | 2017

The 36 V Bipolar:

Edward John Coyne; Shay Whiston; Breandan O hAnnaidh; Donal Peter McAULIFFE; Bill Lane

This paper reports on the optimization of a 36 V complimentary bipolar design by using a new depletion mode field-effect architecture for the collector of the bipolar that greatly expands the boundary of the familiar tradeoffs. This achieves an n-p-n with a measured |β at 1 V x V<sub>a</sub> at 18 V| = |270 x 1100 V|, a JfT at 1 V = 28.7 μAμm<sup>-2</sup>, and |fT at 1 V x BV| = |2.6 GHz x 58 V|, with a p-n-p having a |β at 1 V x V<sub>a</sub> at 18 V| = |250 x 800 V|, a JfT at 1 V = 27.0 μ Aμm<sup>-2</sup>, and |fT at 1 V x BV| = |1.9 GHz x 69 V|. While these performance enhancements appear to offer a lot with little expense, they do serve to reveal an additional tradeoff between β x V<sub>a</sub> x fT x BV x JfT and Linearity. This is where the curvature of the forward output characteristic curves quantified by the extrapolated Early voltage significantly changes over the voltage range |0-10 V|. Through the use of measured silicon results with calibrated TCAD simulations, the physics behind this depletion mode collector design is explained, and using this understanding, it ultimately shows how it is possible to limit the range of the associated nonlinear performance for low collector biases. Then, keeping linearity as a key performance target together with the field-effect architecture, the 36 V bipolar is rebalanced to achieve ann-p-nwitha|β at 1 V x V<sub>a</sub> at 18 V x fT at 1 V x JfT at 1 V x BV x Linearity| = |270 x 220 V x 2.6 GHz x 28.7 μAμm<sup>-2</sup> x 47 V x (0.2-30 V) Linearity|, and a p-n-p with a |β at 1 V x V<sub>a</sub> at 18 V x fT at 1 V x JfT at 1 V x BV x Linearity| = |185 x 180 V x 1.8 GHz x 27 μAμm<sup>-2</sup> x 45 V x (0.2-30 V) Linearity|.


Journal of Micro-nanolithography Mems and Moems | 2011

\beta \times V_{a} \times \text {fT} \times \text {BV} \times \text {JfT} \times

Edward John Coyne

This paper describes the development of a superzone solid immersion diffraction vortex lens and sub-wavelength antireflection surfaces for analyzing dense integrated circuitry through the silicon substrate. The diffractive optic is used with the scanning laser microscope imaging system at a wavelength of 1064 nm. The silicon substrate consists of wafer grade silicon, 10 15 cm −3 P -type, with an integrated memory array at the 90 nm technology node as the target structures. The solid immersion diffractive optic is designed using computer generated holography, and the functionality is simulated using a finite difference time domain numerical method. The blazed phase profile and sub-wavelength structures of the diffractive optic are fabricated using a two step procedure of gray scale gallium implantation with the focused ion beam, followed by the reactive ion etching using CHF 3 chemistry. The developed fabrication conditions for the optical structures investigate implant doses ranging from 0 to 1000 pC μm −2 using the 1000 pA beam current, with etch times from 0 to 25 min. Experimental results demonstrate functional optical vortex lenses that achieve selective suppression of signals from target IC structures to enhance the contrast of the surrounding circuitry. To reduce reflection losses, sub-wavelength, antireflection surfaces targeting the 1064 and 3300 nm wavelengths are investigated. Spatial periods of 140 and 500 nm are achieved, with fill factors of 0.3 to 0.4 over the quarter wavelength antireflective height. For resolution enhancement, a second order superzone solid immersion lens with a numerical aperture of 3.4 is fabricated and demonstrates a 1.6× improvement in image resolution over the first order solid immersion lens with a numerical aperture of 1.7, which in turn achieves a 3.5× improvement over no immersion lens.


bipolar/bicmos circuits and technology meeting | 2017

Linearity Tradeoff

Breandan O hAnnaidh; Edward John Coyne; Bill Lane; Shane Geary

This paper presents a Verilog-A compact model adaptation for a High Voltage SiGe HBT in a DTI on SOI process incorporating characteristic changes observed from a Field Effect Electrode. The output characteristics of the Bipolar are controlled, or “tuned”, by what is effectively an additional terminal. The model proposed is based on MEXTRAM and includes a new terminal node. The main additional effects are captured through the use of empirical formulae, while maintaining the bulk of the original code. The model is validated against DC and AC results from on-wafer Si test structures.


bipolar/bicmos circuits and technology meeting | 2016

Nanofabrication of superzone solid immersion vortex lens and subwavelength antireflection surfaces for enhanced scanning laser imaging

Edward John Coyne; Seamus Lynch; Pat McGuinness; Christine McLoughline; Catriona O'Sullivan; Bill Lane; Larry O'Sullivan; John Liddy

Known to the power industry, there is an increasing functional safety need to isolate delicate control systems from the violent world of the Insulated Gate Bipolar Transistor (IGBT), which has resulted in a growing demand for Digital Isolators. This is where the gate control signal for the IGBT can be coupled across a dielectric barrier, while the barrier itself is capable of withstanding high working voltages and surge events. Preventing the formation of a complete integrated system solution for the end customer is the fact that while the control signal can be coupled across the isolation barrier - the transient power needed to drive the IGBT gate cannot. To solve that problem, this paper describes the development of an innovative IGBT architecture that targets the 1200V voltage node, has a first silicon VCE(SAT) = 2.7V at JC=10Amm-1, provides latch-up immunity, and critically has gate drive capacitances that are over two orders of magnitude smaller, at 0.58pF for every Amp of IGBT current, relative to conventional IGBT architectures that report values in the range of 70 - 150pFA-1 at 25°C. This low input capacitance opens the door for the gate of this IGBT to be directly powered by integrated magnetically coupled isolation coils. For future work, further optimization of the VCE(SAT), and transient switching times are required.


IEEE Transactions on Electron Devices | 2013

A Tunable bipolar: Investigation of effects and a MEXTRAM based VerilogA model adaptation of field effect electrode influenced high voltage sige HBTs

Edward John Coyne

This paper describes the challenges encountered and solutions found to be the problem of developing over-voltage protection for 225 V circuit applications with measured tunable trigger voltages of 100-300 V, measured tunable holding voltages for latch-up immunity of 50-240 V, and corresponding strengths of 8.0-2.4 A Transmission Line Pulse (TLP). The device is engineered using technical computer-aided design and the performance is measured with dc characterization, unpowered TLP, powered and unpowered Electrostatic Discharge (ESD), as well as a 225 V product placement with a 1500-h High Temperature Operating Life lifetime reliability monitor. The final cell enables both 225 V powered and unpowered protection from high voltage switching transients and ESD events.


photonics north | 2004

Low gate drive IGBT enabling direct control through Digital Isolator power

Paul Mannion; Edward John Coyne; Gerard M. O'Connor; Helen Howard; Thomas J. Glynn

The analysis of entrapped debris provides a useful complementary method of investigating the laser ablation mechanism in laser processing of polycrystalline metal samples, in this case stainless steel, using a femtosecond laser (Clark MXR, CPA2001). Morphological investigations of the laser processed areas, for a range of laser fluences and pulse number, were recorded using optical and scanning electron microscopies (SEM) and white light interferometry. Data obtained on ablation rates, ejected particle sizes, and crater morphologies show that ablation changes from a smooth to an explosive process at high fluences, as identified with changes in the material removal mechanisms. In this paper, additional insight is derived from the analysis of the debris generated for metal samples, which can be attributed to laser ablation mechanisms based on vaporization, spallation, phase explosion, and fragmentation.


Archive | 2009

Working 225 V Over-Voltage Protection Cell With Tunable Trigger and Holding Voltages for Latch-Up Immunity

Edward John Coyne; Patrick Martin McGuinness; Paul Malachy Daly; Bernard Patrick Stenson; David J. Clarke; Andrew David Bain; William Allan Lane


Archive | 2006

Analysis of entrapped debris during femtosecond machining of metals

William Allan Lane; Eamon Hynes; Edward John Coyne

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Gerard M. O'Connor

National University of Ireland

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