Bill Lin

Implicit state enumeration of finite state machines using BDD's

The authors propose a novel method based on transition relations that only requires the ability to compute the BDD (binary decision diagram) for f/sub i/ and outperforms O. Couderts (1990) algorithm for most examples. The method offers a simple notational framework to express the basic operations used in BDD-based state enumeration algorithms in a unified way and a set of techniques that can speed up range computation dramatically, including a variable ordering heuristic and a method based on transition relations.<<ETX>>

Power estimation methods for sequential logic circuits

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2/sup N/ where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies. >

Hardware/software co-design of digital telecommunication systems

We reflect on the nature of digital telecommunication systems. We argue that these systems require, by nature, a heterogeneous specification and an implementation with heterogeneous architectural styles. CoWare is a hardware/software co-design environment based on a data model that allows to specify, simulate, and synthesize heterogeneous hardware/software architectures from a heterogeneous specification. CoWare is based on the principle of encapsulation of existing hardware and software compilers and special attention is paid to the interactive synthesis of hardware/software and hardware/hardware interfaces. The principles of CoWare are illustrated by the design process of a spread-spectrum receiver for a pager system.

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits

We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a non-linear system of equations of size N, where the variables correspond to state line probabilities. We show that the approximation method is within 3% of the exact Chapman-Kolmogorov method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies.

Basic Gate Implementation of Speed-Independendent Circuits

Existing methods for synthesis of speedindependent circuits under unbounded delay model have difficulties in combining the generality of formal approach with the practicality of the implementation architectures used at the logic level. This paper presents a characteristic property of the state graph specification, called Monotonous Cover requirement, implying its hazard-free implementation within the standard structure of a two-level SOP logic and a row of latches. The overall synthesis procedure ensures satisfiability of this condition by applying the generalised state assignment approach.

Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications

Deep sub-micron processing technologies have enabled the implementation of new application-specific embedded architectures that integrate multiple software programmable processors (e.g. DSPs, microcontrollers) and dedicated hardware components together onto a single cost-efficient IC. These application-specific architectures are emerging as a key design solution to todays microelectronics design problems, which are being driven by emerging applications in the areas of wireless communication, broadband networking, and multimedia computing. However the construction of these customized heterogeneous multiprocessor architectures, while ensuring that the hardware and software parts communicate correctly, is a tremendously difficult and highly error proned task with little or no tool support. In this paper, we present a solution to this embedded architecture co-synthesis problem based on an orchestrated combination of architectural strategies, parameterized libraries, and software tool support.

A generalized state assignment theory for transformations on signal transition graphs

In this article, we propose a global assignment theory forencoding state graph transformations. A constraint satisfaction framework is proposed that can guaranteenecessary and sufficient conditions for a state graph assignment to result in a transformed state graph that is free of critical races. Performing transformations at the state graph level has the advantage that the requirements imposed on the initial STG are very weak. Unlike previous methods, the initial STG need not be a live, safe, nor a free choice net. The only requirement is that the corresponding initial state graph is finite, connected, and has a consistent state assignment. Hence, a very broad range of signal transition graphs can be synthesized. The transformations achievable using the proposed framework correspond to very complex transformations on signal transition graphs. Even transformations that convert a free choice net into a correct non-free choice net and a 1-safe net into a correct 2-safe net are feasible. Addition of transitions that do not follow the Petri net firing rule is also possible. Even though our method can search a large solution space, we will show that it is possible to solve the problem in an exact way in acceptable CPU times in many practical cases.

Fast and scalable priority queue architecture for high-speed network switches

In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine grained quality of service (QoS) guarantees. Priority queues are used to implement highest-priority-first scheduling policies. Our hardware architecture is based on a new data structure called a pipelined heap, or P-heap for short. This data structure enables the pipelining of the enqueue and dequeue operations, thereby allowing these operations to execute in essentially constant time. In addition to being very fast, the architecture also scales very well to a large number of priority levels and to large queue sizes. We give a detailed description of this new data structure, the associated algorithms and the corresponding hardware implementation. We have implemented this new architecture using a 0.35 micron CMOS technology. Our current implementation can support 10 Gb/s connections with over 4 billion priority levels.

MUSE: a multilevel symbolic encoding algorithm for state assignment

A novel state assignment algorithm, called MUSE (multilevel symbolic encoding), for the encoding of FSMs (finite state machines) targeted for multilevel implementation is presented. Novel methods are discussed for the computation of state pair costs that are based onmultilevel algebraic structures derived from the one hot encoded state machine by purely algebraic techniques. Both Boolean (distance-1 MERGE and consensus) and algebraic (SUB-EXPRESSION EXTRACTION and CO-KERNEL EXTRACTION) operations are used to calculate the encoding affinity of state pairs, and account for face embedding constraints as well. Both heuristic and simulated annealing encoding techniques are used. >

MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines

Minimalist is a new extensible environment for the synthesis and veri cation of burst-mode asynchronous nite-state machines. Minimalist embodies a complete technology-independent synthesis path, with state-of-the-art exact and heuristic asynchronous synthesis algorithms, e.g. optimal state assignment (Chasm), two-level hazard-free logic minimization (Hfmin, Espresso-HF, and Impymin), and synthesis-for-testability. Unlike other asynchronous synthesis packages, Minimalist also o ers many options: literal vs. product optimization, singlevs. multi-output logic minimization, using vs. not using fed-back outputs as state variables, and exploring varied code lengths during state assignment, thus allowing the designer to explore trade-o s and select the implementation style which best suits the application. Minimalist benchmark results demonstrate its ability to produce implementations with an average of 34% and up to 48% less area, and an average of 11% and up to 37% better performance, than the best existing package [38]. Our synthesis-for-testability method guarantees 100% testability under both stuck-at and robust path delay fault models, requiring little or no overhead. Minimalist also features both command-line and graphic user interfaces, and supports extension via well-de ned interfaces for adding new tools. As such, it is easily augmented to form a complete path to technology-dependent logic.