A.R. Newton

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockleys square-law MOS model in the saturation region. Since the model is simple, it can be used to handle MOSFET circuits analytically and can predict the circuit behavior in the submicrometer region. Using the model, closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived. The delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is found that the CMOS inverter delay becomes less sensitive to the input waveform slope and that short-circuit dissipation increases as the carrier velocity saturation effect in short-channel MOSFETs gets more severe. >

Delay analysis of series-connected MOSFET circuits

In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the V/sub DS/ and V/sub GS/ of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2- mu m designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N/sup 2/. The delay dependence on input terminal position for SCMS structures is also described. >

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

The problem of state assignment for synchronous finite-state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations, are addressed. The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize the number of literals in the resulting combinational logic network after multilevel logic optimization. Results over a wide range of benchmarks which prove the efficacy of the proposed techniques are presented. Literal counts averaging 20%-40% less than other state-assignment programs have been obtained. >

A simple MOSFET model for circuit analysis

A simple, general, yet realistic MOSFET model, the nth power law MOSFET model, is introduced. The model can express I-V characteristics of short-channel MOSFETs at least down to 0.25- mu m channel length and of resistance inserted MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the SPICE3 MOS LEVEL3 model. The model parameter extraction is done by solving single variable equations and thus can be done within a second, unlike the fitting procedure with expensive numerical iterations used for the conventional models. The model also permits analytical treatment of circuits in the short-channel region and plays the role of a bridge between complicated MOSFET current characteristics and circuit behavior in the deep-submicrometer region. >

Algorithms for hardware allocation in data path synthesis

Novel algorithms for the simultaneous cost/resource-constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a two-dimensional placement problem of microinstructions in space and time. This formulation readily lends itself to the use of a variety of heuristics for solving the allocation problem. The authors present simulated-annealing-based algorithms which provide excellent solutions to this formulation of the allocation problem. These algorithms operate under a variety of user-specifiable constraints on hardware resources and costs. They also incorporate conditional resource sharing and simultaneously address all aspects of the allocation problem, namely register, arithmetic unit, and interconnect allocation, while effectively exploring the existing tradeoffs in the design space. >

Test generation for sequential circuits

An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state machines with a large number of states have been successfully generated using reasonable amounts of CPU time and close-to-maximum possible fault coverages have been obtained. For very large sequential circuits, an incomplete scan-design approach to test generation has been developed. The deterministic test generation algorithm is again used to generate test for faults in the modified circuit. All irredundant faults can be detected as in the complete scan design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value-in general, a tradeoff exists between the number of memory elements required to be made scannable and the maximum allowed length of the test sequence. >

Relaxation-Based Electrical Simulation

Circuit simulation programs have proven to be most important computer-aided design tools for the analysis of the electrical performance of integrated circuits. One of the most common analyses performed by circuit simulators and the most expensive in terms of computer time is nonlinear time-domain transient analysis. Conventional circuit simulators were designed initially for the cost-effective analysis of circuits containing a few hundred transistors or less. Because of the need to verify the performance of larger circuits, many users have successfully simulated circuits containing thousands of transistors despite the cost. Recently, a new class of algorithms has been applied to the electrical IC simulation problem. New simulators using these methods provide accurate waveform information with up to two orders of magnitude speed improvement for large circuits. These programs use relaxation methods for the solution of the set of ordinary differential equations, which describe the circuit under analysis, rather than the direct sparse-matrix methods on which standard circuit simulators are based. In this paper, the techniques used in relaxation-based electrical simulation are presented in a rigorous and unified framework, and the numerical properties of the various methods are explored. Both the advantages and the limitations of these techniques for the analysis of large ICs are described.

An empirical evaluation of two memory-efficient directory methods

This paper presents an empirical evaluation of two memory-efficient directory methods for maintaining coherent caches in large shared memory multiprocessors. Both directory methods are modifications of a scheme proposed by Censier and Feautrier [5] that does not rely on a specific interconnection network and can be readily distributed across interleaved main memory. The schemes considered here overcome the large amount of memory required for tags in the original scheme in two different ways. In the first scheme each main memory block is sectored into sub-blocks for which the large tag overhead is shared. In the second scheme a limited number of large tags are stored in an associative cache and shared among a much larger number of main memory blocks. Simulations show that in terms of access time and network traffic both directory methods provide significant performance improvements over a memory system in which shared-writeable data is not cached. The large block sizes required for the sectored scheme, however, promotes sufficient false sharing that its performance is markedly worse than using a tag cache.

Exact algorithms for output encoding, state assignment, and four-level Boolean minimization

A novel minimization procedure of prime implicant generation and covering that operates on symbolic outputs, rather than binary-valued outputs, is proposed for solving the output encoding problem. An exact solution to this minimization problem is also an exact solution to the encoding problem. While this covering problem is more complex than the classic unate covering problem, a single logic minimization step replaces O(N-factorial) minimizations. The input encoding problem can be exactly solved using multiple-valued Boolean minimization. An exact algorithm is presented for state assignment by generalizing the proposed output encoding approach to the multiple-valued input case. Four-level Boolean minimization entails finding a cascaded pair of two-level logic functions that implement another logic function, such that the sum of the product terms in the two cascaded functions or truth tables is minimum. Four-level Boolean minimization can be formulated as an encoding problem and solved exactly using the proposed algorithms. Preliminary experimental results are presented which indicate that this approach is significantly more efficient than exhaustive search. Computationally efficient heuristic approaches based on the exact algorithms are proposed for output encoding, state assignment, and four-level Boolean minimization. >

An Algorithm for Optimal PLA Folding

In this paper we present a graph-theoretic formulation of the optimal PLA folding problem. The class of admissible PLA foldings is defined. Necessary and sufficient conditions for obtaining the optimal folding are given. A subproblem of the optimal problem is shown to be NP-complete, and a heuristic algorithm is given which has proven to be effective on a number of test problems.