Bill Vassilakis

A Compact Envelope-Memory Polynomial for RF Transmitters Modeling With Application to Baseband and RF-Digital Predistortion

In this letter, a compact envelope-memory polynomial based model, suitable for forward and reverse modeling of weakly nonlinear wireless transmitters and power amplifiers (PAs) exhibiting electrical memory effects, is presented. This model is implemented in a complex gain based architecture and takes advantage of the dependency of PA nonlinearity on the magnitude of the input signal. Contrary to conventional memory polynomials, the proposed model can be implemented in baseband, as well as in radio frequency, digital predistorters. A 100-W average power transmitter is used for experimental validation of the forward and reverse models. Both forward and reverse modeling results obtained with the proposed model are comparable to that of the conventional memory polynomial.

Synergetic Crest Factor Reduction and Baseband Digital Predistortion for Adaptive 3G Doherty Power Amplifier Linearizer Design

A novel approach for power amplifier (PA) characterization suitable for single iteration digital predistorter synthesis is proposed. This approach consists of synergetic crest factor reduction and baseband digital predistortion to avoid the average power variation at the input of the PA between the characterization and linearization steps. This is achieved by bypassing the crest factor reduction block during the characterization step and by applying it concurrently with digital predistortion in the linearization step. First, the PAs behavior sensitivity to the average input power is evaluated. The limitations of conventional approaches for the PA characterization, in the context of single iteration digital predistortion, are then demonstrated. The performance of the proposed technique is validated experimentally on a 300-W peak PA. The measured improvement of the adjacent channel power ratio at the output of the linearized amplifier is 16 dBc for the conventional approach and 29 dBc for the proposed approach.

Power Amplifiers' Model Assessment and Memory Effects Intensity Quantification Using Memoryless Post-Compensation Technique

A novel approach for power amplifiers static nonlinearity characterization in the presence of memory effects is presented. A subsampling technique is used to reduce the bandwidth of the test signal without changing the waveform characteristics. This cancels the memory effects of the amplifier without affecting its static behavior. Memoryless AM/AM and AM/PM characteristics are measured as a function of the carrier frequency. This points out the contribution of the frequency dependency of the amplifiers static nonlinearity to its behavior under wideband signal drive. A memoryless post-compensation technique is then introduced to accurately assess the performance of several behavioral models. In fact, it is demonstrated that direct comparison of the measured output of the device-under-test with the estimated output does not provide reliable assessment of the model performance. Conversely, memoryless post-compensation efficiently differentiates the performance of these models. To provide a comprehensive approach for model validation and prototype performance evaluation, memory effects intensity metrics are introduced. These metrics are applied to evaluate the memory effects present in a 300-W peak power Doherty amplifier driven by various multicarrier wideband code division multiple access signals.

A Data-Based Nested LUT Model for RF Power Amplifiers Exhibiting Memory Effects

In this letter, a new model is proposed for radio frequency power amplifiers exhibiting memory effects. The model is based on nested look-up tables that compute the estimated amplifier output signal, based on the current input sample and the preceding ones. The model is validated experimentally, using input and output waveforms of a high-power LDMOS based amplifier driven by a multicarrier WCDMA signal. It is shown that the performance of the proposed model is comparable to that of the conventional memory polynomial model. However, the nested look-up table based model significantly reduces the complexity of the identification of the models parameters, as well as the computational complexity in calculating the estimated output signal.

Bias circuit topologies for minimization of RF amplifier memory effects

Memory effects in amplifiers can be described as the dependence of the output signal not only to the instantaneous input, but also to previous inputs. In a system where these effects exist, the linearity of the amplifier is degraded by the DC supply impedance, which is affected by changes in the instantaneous bandwidth of the input signal. The resulting nonlinearity is difficult to remove completely, even by the most sophisticated predistortion techniques. This paper describes a circuit technique that is readily applicable to RF amplifiers designed for wideband applications used with or without a lineariser. The memory effect reduction is achieved by placing transmission zeros in the bias network transfer function. Transmission zeros at the output of device are formed by utilizing the series resonance properties of decoupling capacitors. The frequency response is synthesized to lower and even out the impedance of the bias network over the resulting distortion bandwidth.

Ultra-linear power amplifier characterization using dynamic range extension techniques

The rapid growth of the wireless industry requires more efficient utilization of the available frequency spectrum. This has resulted in requirements for highly linear Multi-Channel Power Amplifiers (MCPAs) to support increases in voice and data traffic. To characterize the resulting ultra-linear MCPAs and to comply with intermodulation levels less than -80 dBc requires measurement systems with dynamic range performance beyond what is currently available. A new instrument, which extends the dynamic range of current distortion measurement systems by at least 25 dB, has been developed to meet this challenge.

Novel approach for static nonlinear behavior identification in RF power amplifiers exhibiting memory effects

In this paper, an experimental approach is proposed to accurately identify, under a modulated signal drive, the memoryless nonlinearity of power amplifiers exhibiting memory effects. It is experimentally demonstrated that, when they are present, memory effects bias the extracted static nonlinearity. Accordingly, the sampling rate of the WCDMA test signal waveform is varied to reduce the signal’s bandwidth. It is shown that this approach minimizes the memory effects contribution to the amplifier’s nonlinear behavior and leads to accurate characterization of the ‘true’ static nonlinearity. The performance of the proposed approach is then assessed through experimental memoryless digital predistortion.

On the effects of the average power of training sequences used to synthesize memory digital predistorters in WCDMA transmitters

In this paper, a study of the effects of the average power of the training sequences used in characterizing the power amplifier on the performance of synthesized memory polynomial digital predistorters is presented. This study was carried out on a 3G 100-Watt peak power amplifier operating over a 12 dB average input power range. The amplifier was characterized over this power range in steps of 1 dB, and the corresponding memory polynomial predistortion function was derived at each operating average power. It was shown that the average power mismatch between the power amplifier and the predistorter degraded the adjacent channel power ratio of the linearized amplifier by up to 9 dB. The predistorters parameters variation with the average input power was then investigated. Consequently, a nonlinear filter bank was proposed to store the memory polynomial coefficients as a function of the average power levels. The memory bank is added to the predistorter along with an average power estimator, in order to maintain the performance of the linearized amplifier over the entire input power range.

Digital predistorter architecture with small signal gain control for highly nonlinear RF power amplifiers

In this paper, a digital predistorter (DPD) architecture is proposed for the linearization of highly nonlinear RF power amplifiers. This digital predistorter architecture uses a complexity reduced and a computationally efficient procedure to synthesis the predistortion function. Unlike conventional digital predistortion architectures that require more than one characterization to get a perfect match between the PAs nonlinearity and that of the DPD, the proposed architecture uses a single characterization and iteratively optimizes the predistortion function performance by controlling the predistorters small signal gain. Experimental validation carried on a highly nonlinear RF power amplifier demonstrates the ability of the predistorters small signal gain control to improve the linearity performance.

Error signal reuse in a feedforward amplifier

In this paper, the concept of frequency selective feedback is examined in the context of feedforward (FFWD) amplifier architecture. In a typical FFWD system, a time-delayed signal that represents the distortion products is injected in anti-phase at the main amplifier output, thus improving the overall intermodulation distortion (IMD) of the system. This signal may also be reused as a feedback signal for improving the uncorrected main amplifier performance. Main amplifier linearity improvement is important in terms of efficiency, size and cost, and can be achieved at a small price in terms of added complexity. This paper presents simulation and measured results that were obtained from a realized system. The practical limitations of this technique are also outlined.