Binhong Li

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N + source). The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer (LET), which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to 0.7 pC/ μ m. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.

Effect of cryogenic temperature characteristics on 0.18-μm silicon-on-insulator devices*

The experimental results of the cryogenic temperature characteristics on 0.18-μm silicon-on-insulator (SOI) metal-oxide-silicon (MOS) field-effect-transistors (FETs) were presented in detail. The current and capacitance characteristics for different operating conditions ranging from 300 K to 10 K were discussed. SOI MOSFETs at cryogenic temperature exhibit improved performance, as expected. Nevertheless, operation at cryogenic temperature also demonstrates abnormal behaviors, such as the impurity freeze-out and series resistance effects. In this paper, the critical parameters of the devices were extracted with a specific method from 300 K to 10 K. Accordingly, some temperature-dependent-parameter models were created to improve fitting precision at cryogenic temperature.

Process variation dependence of total ionizing dose effects in bulk nFinFETs

Abstract The electrical characteristics of bulk nFinFETs after total-ionizing-dose (TID) irradiation were experimentally evaluated with respect to the process variation (PV). The inconsistent transfer characteristics, particularly the different threshold voltage shifts under an identical bias condition and irradiation dose, were investigated through technology computer aided design (TCAD) simulation, considering the shallow trench isolation (STI) footing and the asymmetrical sidewall. The influence that the bias condition had, as an important factor including ON, OFF, and transmission gate (TG), is included in this paper to better illustrate the PV dependence. The HfO 2 high-ĸ metal gate, the STI, and the PV dependent geometry were some of the influences that occurred within the degradation of electrical performances as the TID increased. A radiation-hardness strategy was proposed in order to improve the electrical properties of the FinFET devices in the radiation environments.

The total ionizing dose response of leading-edge FDSOI MOSFETs

Abstract In this paper, the total ionizing dose (TID) response of Ultra-Thin SOI (UTSOI) transistor is presented. TID experiments were performed on both NMOS and PMOS transistors under three different bias configurations (ON-state, OFF-state, TG-state). The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors. And the TID response variability caused by bias configuration during irradiation is small in UTSOI transistors. Besides this, the impact of back gate bias on TID response is also investigated. When a positive back bias is applied on NMOS transistor to achieve better performance, the threshold voltage degradation caused by TID becomes worse. While the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance. An explanation of back gate impact on front gate TID response is given with TCAD simulation.

Complexity of the total dose radiation response of fully depleted silicon-on-insulator NMOSFETs

With bias conditions changed during irradiation, the bias dependence of the total dose radiation response of fully depleted (FD) silicon-on-insulator (SOI) n-channel MOS transistors (NMOSFETs) is investigated preliminarily. It is found that the threshold voltage shift of the FD SOI NMOSFETs as a function of total dose exhibits an abrupt inverse change, namely, a unexpected rapid reduction, with increasing total dose, when the bias condition is changed from OFF-state into transmission gate (TG). It is also found that it is not always effective to reduce the total dose sensitivity of the tested transistors by applying a negative voltage to their back gates during irradiation. In addition, the rebound of the threshold voltage shift has been observed clearly with dose for the transistors biased using both the OFF-state and the TG during irradiation, which can be partly attributed to the radiation induced electron traps located at the interface between the silicon film and buried oxide (BOX).

Improved single-event hardness of trench power MOSFET with a widened split gate

In this paper, a new 200V power MOSFET structure with a widened split gate trench to enhance single-event radiation hardness is proposed and studied by numerical simulation. The new MOSFET not only offers a great Rds(on)×Qgd FOM, but also 55.3% wider radiation-hard Safe Operating Area (RHSOA) than the conventional trench MOSFET and split gate structure. The RHSOA advantage of the new device structure is due to the elimination of P-well region beneath the N+ source to almost completely suppress the influence of the parasitic NPN transistor, which is caused by the widened gate trench structure. In addition, this fabricating technology is compatible with the standard trench fabricating technology and the structure feature can be applied for all voltage ratings device with trench gate design. This new power MOSFET structure provides a great potential in space and aerospace power application.

Effect of shell-tube dimensions on the reliability of power VDMOS by temperature cycling

With the improvement of packaging technology, small packaging type is gradually becoming mainstream. Packaging dimension has a significant influence on the performance and reliability of power Vertical Double diffused MOSFET (VDMOS) device. In this paper, the thermal stress of different shell-tube dimensions in power VDMOS device is simulated by finite element methods using ANSYS software. The simulation results show that the solder joint between the power VDMOS chip and the shell was under the maximum thermal stress, and an inverse relationship was found between shell-tube dimensions and the thermal stress of the solder joint. In order to validate the simulation conclusion for the inverse relationship, this paper selected TO-257 and TO-254 package type for the same VDMOS chip. The shell-tube dimensions of TO-254 is larger than TO-257. The temperature cycling experiment was carried out with five samples drawn in each package type. The author found that the on-state resistance of the TO-257 package increased significantly after 500 cycles, but the TO-254 package was almostly unchanged. The evolution of the on-state resistance would be explained by the thermo-mechanical effects. Furthermore, some voids were observed in the solder joint of the TO-257 package after the temperature cycling experiment according to the results of scanning acoustic microscope (SAM), which is mean that the solder of the TO-257 package severely degrade after temperature cycling. Due to the smaller shell-tube dimensions of the TO-257 package, the larger thermal stress of the solder joint is generated in temperature cycling. It has been demonstrated that the ANSYS software simulation results were in accord with the experimental results which indicate that the shell-tube dimensions can seriously impact on the solder joint of power VDMOS device.