Jiantou Gao

A radiation-hardened SOI-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 m partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary- scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 10 11 rad(Si)/s and a neutron fluence immunity of 1 10 14 n/cm 2 .

DSOI FET - A novel TID tolerant SOI transistor

Charge trapping in the buried oxide can lead to serious back-channel leakage and make SOI (Silicon-on-Insulator) transistors more sensitive to total dose radiation. In this paper, a new DSOI (Double SOI) transistor is proposed, which utilizes the method of back-gate biasing to force an external electric field, and then depress the back channel formation during total dose irradiation. The simulation and testing results both indicate that, for a given structure, when a -3V bias is applied to the back-gate, the DSOI transistor can tolerant a total dose radiation of 500k rad(Si). This methodology fits all kinds of SOI MOSFETs, especially for the Fully-Depletion SOI transistors. With commercial (not especially hardened) buried oxide, DSOI device can have better radiation hardening performance than its both companions - FDSOI and PDSOI transistors.

A 14-bit wide temperature range differential SAR ADC with an on-chip multi-segment BGR

A 14-bit low power self-timed differential successive approximation (SAR) ADC with an on-chip multi-segment bandgap reference (BGR) is described. An on-chip multi-segment BGR, which has a temperature coefficient of 1.3 ppm/°C and a thermal drift of about 100 μV over the temperature range of −40 to 120 °C is implemented to provide a high precision reference voltage for the SAR ADC. The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system. Self-timed bit-cycling is adopted to enhance the time efficiency. The 14-bit ADC was fabricated in a TSMC 0.13 μm CMOS process. With the on-chip BGR, the SAR ADC achieves an SNDR of 81.2 dB (13.2 ENOB) and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from −40 to 120 °C.

A low power and radiation-tolerant FPGA implemented in FD SOI process

A 330,000 gate field programmable gate array (FPGA) VS12C fabricated on 0.2μm full-depletion silicon-on-insulator (FD SOI) process is presented and the test results indicate this chip has the lower power and higher tolerance to radiation compared with Xilinx radiation-hardened XQVR300 chip implemented on 0.22μm epitaxial silicon. This paper demonstrates the benefit of the FD SOI technology on low power and radiation-tolerant FPGA circuit design.

The total ionizing dose response of leading-edge FDSOI MOSFETs

Abstract In this paper, the total ionizing dose (TID) response of Ultra-Thin SOI (UTSOI) transistor is presented. TID experiments were performed on both NMOS and PMOS transistors under three different bias configurations (ON-state, OFF-state, TG-state). The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors. And the TID response variability caused by bias configuration during irradiation is small in UTSOI transistors. Besides this, the impact of back gate bias on TID response is also investigated. When a positive back bias is applied on NMOS transistor to achieve better performance, the threshold voltage degradation caused by TID becomes worse. While the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance. An explanation of back gate impact on front gate TID response is given with TCAD simulation.

Complexity of the total dose radiation response of fully depleted silicon-on-insulator NMOSFETs

With bias conditions changed during irradiation, the bias dependence of the total dose radiation response of fully depleted (FD) silicon-on-insulator (SOI) n-channel MOS transistors (NMOSFETs) is investigated preliminarily. It is found that the threshold voltage shift of the FD SOI NMOSFETs as a function of total dose exhibits an abrupt inverse change, namely, a unexpected rapid reduction, with increasing total dose, when the bias condition is changed from OFF-state into transmission gate (TG). It is also found that it is not always effective to reduce the total dose sensitivity of the tested transistors by applying a negative voltage to their back gates during irradiation. In addition, the rebound of the threshold voltage shift has been observed clearly with dose for the transistors biased using both the OFF-state and the TG during irradiation, which can be partly attributed to the radiation induced electron traps located at the interface between the silicon film and buried oxide (BOX).

Experimental study of single event upset and single event latch-up in SOI SRAM

Dielectric isolation of silicon on insulator (SOI) technology allows circuits to be designed that have reduced single event upset effects and are free from latch-up. For these reasons, SOI technologies are well suited for space applications. In this paper, we investigated both single event upset (SEU) and single event latch-up (SEL) effects of 512k bits SRAMs fabricated in SOI technology. The linear energy transfer (LET) of heavy ions used in the radiation experiment range from 32.4 to 99.8MeV-cm2 /mg. It is shown that devices fabricated in SOI technology which are radiation hardened through advanced and proprietary design, layout and process hardening techniques should exhibit high SEU levels(above 63.7MeV-cm2/mg). Besides, the devices are SEL immune.

Total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator pMOSFETs

The total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator (SOI) pMOSFETs have been studied by comparing them with those of the back transistor of SOI nMOSFETs fabricated on the same wafer. The transistors were irradiated by 60Co γ-rays with various doses and the front transistors were biased in a Float-State and Off-State, respectively, during irradiation. The total dose radiation responses of the back transistors were characterized by their threshold voltage shifts. The results show that the total dose radiation response of the back transistor of SOI pMOSFETs, similar to that of SOI nMOSFETs, depends greatly on their bias conditions during irradiation. However, with the Float-State bias rather than the Off-State bias, the back transistors of SOI pMOSFETs reveal a much higher sensitivity to total dose radiation, which is contrary to the behavior of SOI nMOSFETs. In addition, it is also found that the total dose radiation effect of the back transistor of SOI pMOSFETs irradiated with Off-State bias, as well as that of the SOI nMOSFETs, increases as the channel length decreases. The annealing response of the back transistors after irradiation at room temperature without bias, as characterized by their threshold voltage shifts, indicates that there is a relatively complex annealing mechanism associated with channel length, type, and bias condition during irradiation. In particular, for all of the transistors irradiated with Off-State bias, their back transistors show an abnormal annealing effect during early annealing. All of these results have been discussed and analyzed in detail by the aid of simulation.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field- programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 m partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 10 11 rad(Si)/s, and a neutron fluence immunity of 1 10 14 n/cm 2 .

Design studies on the ERL-FEL test facility at IHEP, Beijing

A proposed compact ERL test facility at THEP, Beijing, is presented in this paper, and includes the design parameters, the essential lattice, and the key components features, such as the photocathode DC gun and the CW superconducting accelerating structures. Some important beam physics issues such as the space charge effect, the coherent synchrotron radiation (CSR) effect and the beam break-up (BBU) effect are briefly described with the simulation results.