Bo Luo

A novel substrate-assisted RESURF technology for small curvature radius junction

A novel substrate-assisted (SA) RESURF technology aiming at improving off-state breakdown voltage (BV) of PN junction with small curvature radius is proposed and experimentally demonstrated in this paper. The SA RESURF technology not only realizes small curvature radius in the fingertip region, but also reduces electric field concentration in the curved metallurgical junction. Low-doped P-substrate, which increases depletion of the small curvature radius junction and reduces electric field concentration in the curved metallurgical junction, is adopted in the source fingertip region. Owing to the existence of low-doped P-substrate, the abrupt PN junction with small curvature radius is adjusted to low-doped PN junction with large curvature radius. The SA RESURF technology can be widely applied to lateral high voltage devices with small curved junction, especially to lateral super junction devices. A CBSLOP-LDMOS with the proposed SA RESURF technology has been developed. The experimental results show that the CBSLOP-LDMOS exhibits off-state BV of 700 V and specific on-resistance (Ron, sp) of 142 mΩ·cm2.

Deep trench SOI LIGBT with enhanced safe operating area

A novel deep trench SOI LIGBT with enhanced safe operating area has been proposed. Deep trench gate electrode, reaching buried oxide layer, has been directly introduced for achieving low on-resistance. Heavily doped p+ region at the emitter side, which sandwiches between the n-drift region and n+ emitter region, is provided as holes bypassing path for ensuring enhanced forward biased safe operating area. Some of holes will flow from the n-drift to the p+ emitter without flowing through the pwell layer directly. On the other hand, the portion of the n-drift region which underlies the pwell is fully depleted at a relatively low voltage, thus preventing the voltage across the trench gate oxide from becoming too high and causing less reliable and stable problems. This JFET pinch-off effect keeps any hot-carrier injection (HCI) away from the sensitive gate oxide, providing HCI performance far superior to conventional LIGBT devices.

High voltage SJ-pLDMOS with Variation Lateral Doping drift layer

This paper reports a novel Super Junction pLDMOS (SJ-pLDMOS) with charge-balanced SJ region at the surface of Variation Lateral Doping (VLD) drift region. SJ region provides a low on-resistance path in the ON-state and keeps charge balance approximately when the doping concentration of p pillars is slightly higher than that of the n pillars during the OFF-state. A significant reduction of the specific on-resistance for a given Breakdown Voltage (BV) can be achieved by using a high aspect ratio of the SJ pillars. Simulation results show that the SJ-pLDMOS with Ld of 35µm exhibits BV of 582V and Ron,SP of 210mΩ.cm2, yielding to a power Figure Of Merit (FOM) of 1.6 MW/cm2. These excellent device performances make the proposed SJ-pLDMOS a promising candidate for level shift circuit.