Bo Zhang

Polycrystalline silicon films and thin-film transistors using solution-based metal-induced crystallization

Polycrystalline silicon (poly-Si) films consisting of dish-like and wadding-like domains were obtained with solution-based metal-induced crystallization (SMIC) of amorphous silicon. The Hall mobility of poly-Si was much higher in dish-like domains than in wadding-like domains. Thin-film transistors (TFTs) have been prepared using those two kinds of poly-Si films as the active layer, followed by the phosphosilicate glass (PSG) nickel gettering. The field effect mobility of dish-like domain poly-Si TFTs and wadding-like poly-Si TFTs were 70~80 cm2/Vmiddots and 40~50 cm2/Vmiddots, respectively. With a multi-gate structure, the leakage current of poly-Si TFTs was reduced by 1 to 2 orders of magnitude. In addition, the gate-induced drain leakage current (GIDL) and uniformity of the drain current distribution were also improved. P-type TFTs fabricated using SMIC exhibited excellent reliability

Polysilicon Thin Film-Transistors With Uniform and Reliable Performance Using Solution-Based Metal-Induced Crystallization

The authors studied electrical characteristics of p-channel polycrystalline silicon thin-film transistors (TFT) fabricated by solution-based metal-induced crystallization (SMIC). In particular, the effect of annealing conditions was systematically investigated. The current-voltage characteristics show that the performance of TFTs was dominated by the SMIC process rather than the annealing temperature up to 630 degC. All the devices exhibited good uniformity after annealing. The effects of gate stress and self-heating stress were also studied. The device performance was not affected by both stresses for all devices, p-channel SMIC poly-Si TFT has high performance, good uniformity, and satisfactory reliability with a process temperature < 600 degC

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBTI) or electron injection (EI) is observed under -Vg or -Vd only stress, respectively, no typical hot carrier (HC) degradation can be identified under high -Vd stress combined with either low or high -Vg stress. Instead, mixed NBTI and EI degradation is observed under combined low -Vg and -Vd stresses; and combined degradation of NBTI and HC occurs under high -Vd and moderate -Vg stresses. NBTI is the dominant mechanism in both cases. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTs degradation.

A comprehensive analytical on-current model for polycrystalline silicon thin film transistors based on effective channel mobility

A comprehensive analytical ON-state drain current model for poly-Si thin film transistors (TFTs) is developed to accurately fit both transfer and output characteristics of either low or high temperature processed poly-Si TFTs in both n- and p-types, with the same unified analytical form. The model is physical explicitly based and mathematically accurate, with no artificial factors introduced. To accomplish this, (1) the most appropriate model precisely describing the gate voltage dependent mobility degradation effect in poly-Si TFTs is determined from three previously employed models; (2) grain boundary barrier controlled carrier conduction model is adequately incorporated; and (3) a mathematically accurate analytical form for drain current is derived based on gradual channel approximation by introducing a new fitting parameter to describe the effective average channel mobility. Channel length modulation effect is introduced in modeling output characteristic. Applicability and accuracy of the model are de...

P-17: Metal Induced Continuous Zonal Domain Polycrystalline Silicon and Thin Film Transistors

Metal induced polycrystalline silicon (poly-Si) films composing of continuous zonal domain (CZD) in exactly same width have been obtained through pre-defined crystalline nucleation lines (CNL) on a nano-layer of silicon dioxide. Employing this technology, the impact of glass substrate shrinking on subsequent alignment process is determined. Additionally, the crystallization process is strictly controllable and the annealing time is shorter than one hour. P-channel thin film transistors (TFTs) built on CZD poly-Si exhibit high performance and high uniformity.

Degradation of solution based metal induced laterally crystallized p-type poly-Si TFTS under DC bias stresses

Device degradation of solution based metal-induced laterally crystallized (MILC) p-type poly-Si thin film transistors (TFTs) is studied under DC bias stresses, which is found to be dominated by negative bias temperature instability (NBTI) mechanism. While standard NBTI or electron injection (EI) is observed under -Vg or -Vd only stress, respectively, a mixed NBTI and EI degradation is observed under combined low -Vg and -Vd stresses. Under high -Vd and moderate -Vg stress, pure hot carrier (HC) degradation cannot be observed, but a combined degradation of NBTI and HC occurs. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTspsila degradation.

Competitive antiferromagnetic and ferromagnetic coupling in a CrSe/Fe/GaAs(111)B structure

A novel transition from the negative exchange bias (NEB) to the positive exchange bias (PEB), due to coexistent and competitive ferromagnetic and antiferromagnetic coupling in a molecular-beam-expitaxy-grown CrSe/Fe/GaAs(111)B structure, is described. The source of the unusual PEB effect was found to originate from the interface at the hetero-junction of Fe/GaAs(111)B while the NEB effect resulted from the CrSe/Fe bilayer structure. Phenomenological models are presented to explain the mechanism of the PEB effect and the varying asymmetry of the magnetic hysteresis of this structure as a function of the measured temperature.

Molecular-beam-epitaxy-grown CrSe∕Fe bilayer on GaAs(100) substrate

A novel CrSe∕Fe bilayer structure has been fabricated on a GaAs (100) substrate by the molecular beam epitaxy technique. Microstructural characterizations have revealed that the Fe layer is a single-crystalline bcc structure with the orientation relationship of (100)Fe‖(100)GaAs, while the top CrSe layer shows four preferred hexagonal domains with their c axis each along one of the four upward-pointing ⟨111⟩ directions of the underlying Fe lattice. The magnetic hysteresis loops of this bilayer structure measured by a superconducting quantum interference device magnetometer demonstrate a strong exchange bias effect with a negative exchange bias field as high as −48.4Oe at 5K. The magnetization reversal process shows an abrupt transition nature at temperature from 5to300K. An enhancement of the coercivity not accompanied by the exchange bias field was observed at temperature higher than and well above the blocking temperature. We have interpreted these observations based on the well-established exchange spr...

P-10 Post-Crystallization of Metal-Induced Laterally Crystallized Poly-Si with YAG Laser

Post-crystallization heat-treatment of metal-induced laterally crystallized polycrystalline silicon thin film using YAG solid-state laser is characterized. It is found that both the material quality and the TFT performance are related to the laser-treatment condition. The amorphous silicon fraction remaining in the polycrystalline thin film can be reduced and the performance of the thin-film transistors fabricated on the laser-treated thin film under an optimized condition can be greatly improved.