Bodo Hoppe

Verification for fault tolerance of the IBM system z microprocessor

IBM System z· processors are known for their industry leading Reliability, Availability and Serviceability (RAS). The hardware is designed to support a high resilience against errors and the ability to recover from errors maintaining a valid architectural state. This paper describes the thorough verification effort required to prove that the fault tolerance of the IBM System z processor core matches the high expectations prior to design tape-out. This paper proposes a multifaceted verification methodology to cover the various aspects of verifying correct error detection, isolation and recovery. Soft errors enlarge the state space of a design significantly. This provides a significant challenge to the functional verification environment in order to tolerate the fails and to expect architectural compliance. Several fault injection mechanisms are discussed. A special focus is on the novel methodology of Comprehensive Fault Injection (CFI) used to validate and improve the dependability characteristics of the processor core, providing improved Soft Error Resilience (SER). Feedback of the results and measurements of the efficiency and functional coverage are an integral part of the overall methodology, allowing the smart use of the available compute resources.

Design and verification of the IBM system z10 I/O subsystem chips

In this paper, we discuss the microarchitecture, design, and S. Junghans verification of two IBM System z10™ I/O (input/output) chips: the z10™ hub chip, an InfiniBand™ host channel adapter with IBMproprietary enhancements, and the InfiniBand memory bus adapter (MBA) chip, an InfiniBand-to-self-timed-interface fanout chip for attaching legacy I/O. Designing and verifying these chips presented many challenges. We describe our transaction- and packet-tracking concepts and the use of communication groups that emulate the behavior of logical partitions and their role in handling error and recovery cases. A novel technique has been employed to ensure that design implementation and architectural register definitions are consistent in a fully automated approach. Finally, we describe our approach to improving self-test coverage, which is based on an automated process of test-point insertion.

Functional verification of a frequency-programmable switch chip with asynchronous clock sections

An integral part of the IBM eServerTM z990 I/O subsystem is the self-timed interface (STI) switch chip. The STI switch is an application-specific integrated circuit (ASIC) designed to provide high I/O connectivity and high bandwidth within the system. The complexity of the functional verification of the STI switch chip is inherent in the implementation of seventeen logical clock domains and the support of six different STI interfaces with programmable frequencies. The logic within these clock domains is connected via asynchronous interfaces. This paper describes the methodology to verify the functionality of the switch chip with various STIs by introducing a combination of verification techniques. This involves random biased stimulus generation, automated result prediction checking, and the use of cycle simulation to stress the logical design. The cycle simulation required new techniques to model equivalent behavior in order to verify the correct integration of nondigital components on the chip. Advanced methods were implemented to ensure correctness of the frequency-dependent design units and functionality across the asynchronous interfaces. A single verification environment was developed, providing the flexibility to seamlessly support the different levels of design abstraction and uncover the design errors at the appropriate level.

Gating Aware Error Injection

Error injection is one of the most commonly used techniques for estimating the reliability of a given hardware design. While error injection in dynamic simulation is widely used in the industry, other methods exist as well, e.g. hardware error injection and fault-tolerance analysis using formal verification. As covering the entire space of all possible fault injections is impractical, nearly all workload-based error injection methods (e.g. simulation or emulation techniques) use a statistical approach for error injection, i.e. they only inject a fraction of all possible faults. As a result, the statistical fault injection approach is much more efficient in characterizing the overall reliability of the design than in finding particular reliability-related bugs. On the other hand, the formal-based approach guarantees full coverage of the design space, including under all possible faults, granted the formal analysis can be completed. However, performing formal verification on design hierarchies with error detection and recovery logic is usually unfeasible. To address the challenge of effectively finding reliability-related bugs on large industrial designs, this paper proposes a novel approach which is aimed at finding a particular kind of design bugs related to gating conditions which correspond to error detection logic. We present an automated method for identifying those gating conditions and generating a gating-aware fault injection module. Experimental results on a real microprocessor arithmetical unit demonstrates the effectiveness of our method in finding real design bugs using relatively small amount of error injection tests.

IBM system z functional and performance verification using X-Gen

In the IBM System z10trade project, new hardware components such as a processor core, memory and IO subsystem as well as new packaging components have been designed. In this paper we describe how functional hardware verification has been applied to verify the correctness of system related functions. A huge challenge is to prove that the system performance with respect to bandwidth and latency actually matches the predictions as well as the actual prototypes. This paper describes a new method that has been introduced in order to verify the system performance using simulation of RTL models. The paper further describes the application of a model-based random test case generator named X-Gen to provide complex testing scenarios, intelligent background noise, and expected results. It concludes with the results of the verification approaches with respect to finding functional and performance related hardware inefficiencies during the design implementation phase.