Brian W. Thompto

Functional verification of the IBM system z10 processor chipset

This paper describes the comprehensive verification effort of the IBM System z10™ processor chipset, which consists of the z10™ quad-core central processor chip and the companion z10 symmetric multiprocessor (SMP) chip. The z10 processor chipset represented a significant redesign of its predecessor and thus presented a new challenge to ensure complete functional correctness of the product before the construction of actual system hardware. The z10 microprocessor pipeline was completely redesigned to support a doubling of the operating frequency. It also includes new hardware performance features, such as enhanced branch prediction, a reoptimized cache hierarchy, hardware-based prefetching, and a hardware implementation of decimal floating-point arithmetic in IEEE formats. In addition, there were significant hardware changes in the SMP storage hierarchy for optimized data latency performance. These changes include a new system topology, interprocessor book protocol, larger SMP size, and various aggressive cache ownership schemes. Key verification innovations are described, and a direct relationship to improved z10 system quality is provided for most cases.

Verification of Transactional Memory in POWER8

Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.

POWER9: Processor for the cognitive era

This article consists only of a collection of slides from the authors conference presentation on the POWER9 processor.

Verification for fault tolerance of the IBM system z microprocessor

IBM System z· processors are known for their industry leading Reliability, Availability and Serviceability (RAS). The hardware is designed to support a high resilience against errors and the ability to recover from errors maintaining a valid architectural state. This paper describes the thorough verification effort required to prove that the fault tolerance of the IBM System z processor core matches the high expectations prior to design tape-out. This paper proposes a multifaceted verification methodology to cover the various aspects of verifying correct error detection, isolation and recovery. Soft errors enlarge the state space of a design significantly. This provides a significant challenge to the functional verification environment in order to tolerate the fails and to expect architectural compliance. Several fault injection mechanisms are discussed. A special focus is on the novel methodology of Comprehensive Fault Injection (CFI) used to validate and improve the dependability characteristics of the processor core, providing improved Soft Error Resilience (SER). Feedback of the results and measurements of the efficiency and functional coverage are an integral part of the overall methodology, allowing the smart use of the available compute resources.

Key advances in the presilicon functional verification of the IBM zEnterprise microprocessor and storage hierarchy

This paper highlights key advances in the presilicon verification effort of the IBM zEnterprise® 196 (z196) microprocessor and storage hierarchy. It focuses on the unique set of verification challenges as well as the process innovations that address them. At the time of product launch, the z196 system represented the industrys fastest and most scalable enterprise system, with up to 80 customer-configurable out-of-order core processors operating at 5.2 GHz. In addition to offering industry-leading performance, the z196 system builds upon its leadership in reliability by introducing a new redundant array of independent memory (RAIM) technology into its memory subsystem. The new product features in this system drove innovations in all aspects of processor functional verification, including stimulus generation, functional checking, debugging, and coverage. A new hybrid RAIM verification methodology, which includes both formal and random methods, is described. Many process and methodology improvements were made to improve developmental collaboration across a global team. These enhancements include a simulation development environment that uses common shared components across functional partitions, as well as a shared cache loader that was used across multiple environments. We also present a self-configuring test-case generation process that focused on the coverage of functional stimulus.

IBM Power9 Processor Architecture

The IBM Power9 processor has an enhanced core and chip architecture that provides superior thread performance and higher throughput. The core and chip architectures are optimized for emerging workloads to support the needs of next-generation computing. Multiple variants of silicon target the scale-out and scale-up markets. With a new core microarchitecture design, along with an innovative I/O fabric to support several accelerated computing requirements, the Power9 processor meets the diverse computing needs of the cognitive era and provides a platform for accelerated computing.