Bong Hyuk Park

Analysis of High-Efficiency Power Amplifier Using Second Harmonic Manipulation: Inverse Class-F/J Amplifiers

In this paper, an analysis of a power amplifier manipulated using a second harmonic (PA-2HM) is described using a remarkable correlation between the fundamental and second harmonic impedances. The output loading condition, made up of an optimum fundamental impedance mapped to the conditional second harmonic reactance, allows us to achieve a high-efficiency power amplifier (PA) with a simple output matching circuit. For the analysis, the output voltage and current waveforms are modeled in terms of their output loading in order to extend the output power and efficiency. Specific PA-2HM cases, inverse Class-F and Class-J modes, are analyzed using different second harmonic reactance conditions. The allowable second harmonic reactance for maintaining maximum efficiency has been found to be spread throughout a wide range. To justify the analysis, a harmonic load-pull simulation and measurement are conducted and compared with analysis results. For verification, a commercially available 60-W gallium-nitride (GaN) device was used for different types of PA (inverse Class-F and Class-J) with appropriate second harmonic impedance. In terms of the output power and drain efficiency, the measured results are in good agreement with not only computer-aided design simulations, but also with our analysis and load-pull results.

20-MHz bandwidth continuous-time delta-sigma modulator for EPWM transmitter

A 1.5-bit 20-MHz bandwidth continuous-time delta-sigma modulator (CT-DSM), which is suitable for envelope pulse-width modulation (EPWM) transmitters, is presented. To compensate the process-voltage-temperature variation, a resistor calibration method is proposed. The proposed calibration scheme improves a signal-to-quantization-noise-ratio (SQNR) by 18%. The switched capacitor digital-to-analog converter (DAC) and tri-level output DAC are adopted to improve non-ideal effects and implement multi-level encoding, respectively. Over 44 dB SQNR has been achieved for all corner simulation condition with an oversampling ratio of 13.056 and 20-MHz of bandwidth. The power consumption of the modulator is 11.6 mW from the 1.08 V supply. 1.74% of error vector magnitude can be obtained for a 20 MHz LTE signal with a 9.7 dB peak-to-average power ratio.

Design of a tunable fully differential GHz range Gm-C lowpass filter in 0.18 /spl mu/ m CMOS for DS-CDMA UWB transceivers

Design of a fully differential sixth order GHz range gm-C lowpass filter for DS-CDMA UWB (ultra wideband) transceivers is presented. The filter is composed of three identical cascaded biquad sections. The core of the filter is isolated from the source resistance by a folded cascode input stage. An outer negative feedback loop is used to lower the source resistance seen by the core of the filter and extend the bandwidth to a GHz range. Schemes for near orthogonal tuning of bandwidth and passband gain are described and verified. Peaking in the passband is maintained low to avoid distortion and reduced linearity. The proposed lowpass filter is designed in TSMC 0.18 mum CMOS process. Post layout simulations show that the filter bandwidth is tunable over 600 MHz from 800 MHz to 1.4 GHz and the passband gain is tunable over 6 dB, while the passband peaking is maintained below 2 dB. The filter consumes 24.2 mW under supply voltage of 1.8 V

Hybrid Current-Mode Class-S Power Amplifier With GaN Schottky Diode Using Chip-On-Board Technique for 955 MHz LTE Signal

This paper presents a gallium nitride (GaN)-based hybrid current-mode class-S (CMCS) power amplifier (PA) using a bandpass delta-sigma modulator (BPDSM) for a 955-MHz LTE signal. To enhance the drain efficiency of the CMCS PA, the chip-on-board (COB) technique, which can reduce the external parasitic components of the packaged transistor and allow fast switching operation at high frequencies by minimizing distortion of the pulse waveform, is adopted. Also, GaN Schottky barrier diodes are fabricated in-house to protect the switching transistor against the high negative voltage swing. The differential output filter and balun composed of lumped LC resonators are integrated at the back of the switching transistor to extract amplified LTE signal from the output rectangular waveform, and the fabricated CMCS PA is measured and analyzed at four different states of BPDSM according to the coding efficiency from different input power level to obtain higher power and efficiency. Finally, a cavity bandpass filter (BPF) is added to the output circuit for a more accurate reduction of the harmonics and out-of-band noise signals to enhance system efficiency. From the measured results for an 8.5-dB PAPR 3 G LTE 10-MHz input signal, the proposed CMCS PA has a maximum average output power of 37.61 and 30.78 dBm, and the resulting drain efficiencies of 33.3% and 38.6% with the drain voltage of 19 and 7 V, respectively.

Loop stability compensation technique for continuous-time common-mode feedback circuits

A loop stability compensation technique for continuous-time common-mode feedback (CMFB) circuits is presented. A Miller capacitor and nulling resistor in the compensation network provide a reliable and stable operation of the fully-differential operational amplifier without any performance degradation. The amplifier is designed in a 130 nm CMOS technology, achieves simulated performance of 57 dB open loop DC gain, 1.3-GHz unity-gain frequency and 65° phase margin. Also, the loop gain, bandwidth and phase margin of the CMFB are 51 dB, 27 MHz, and 76°, respectively.

Advanced Class-S transmitter with tri-level delta-sigma modulator

An advanced Class-S transmitter based on a tri-level delta-sigma modulator (DSM) is presented. The second order DSM shows a signal-to-noise and distortion ratio (SNDR) of 44.7 dB and a spurious-free dynamic range (SFDR) of 63.6 dB with a 3.1-MHz sinusoidal input at 522.24-MS/s using an offset cancellation scheme. The proposed technique improves the SFDR and SNDR over 10 dB and 3 dB, respectively. The proposed scheme can effectively control the input referred offset voltage of the DSM, resulting in the improvement of spectrum efficiency. The power consumption of the modulator is 13.4 mW from a 1.2 V supply. Measurements with a mixer show that the proposed modulator modulates a 10-MHz long-term evolution signal which has an 8.5 dB peak-to-average ratio with 3.30 % error vector magnitude and 38.7 dB adjacent channel leakage ratio at 2.6 GHz.

Possibility verification of drone detection radar based on pseudo random binary sequence

This paper presents the possibility verification of a drone detection radar based on pseudo random binary sequence (PRBS). It contains the design of a probing signal and resultant specifications of the radar, measurement setup using commercial signal generator/analyzer and antennas, and laboratory/outdoor measurements. Measurements in the 2 GHz band with 6 dBm transmit condition show the drone detection at the range over 100 m.

Highly efficient Doherty amplifier with peaking cell controlled using optimized shaped gate voltage

In this paper, the optimum gate control for a peaking cell of a Doherty amplifier is proposed. The proposed gate voltage waveform based on a variation in transcoductance provides a sufficient fundamental current for a peaking cell, which is relevant to the performance of a carrier cell. For further verification, a Doherty amplifier controlled by the proposed method and targeting a 3G LTE base station at 2.6 GHz has been fabricated using a commercially available 120 W GaN (Gallium Nitride) device. The amplifier provides a drain efficiency of 49.2% at an average output power of 45.6 dBm with an 8.5 dB PAPR signal maintaining an adjacent channel leakage power ratio of −48 dBc through digital pre-distortion (DPD) functionality.

A CMOS Multi-LO Frequency Synthesizer Block for MB-OFDM UWB Systems

A multi-LO frequency synthesizer block for MB-OFDM UWB systems is proposed, which is implemented in 0.18 mum CMOS technology. The proposed frequency synthesizer can provide three LO tones and quadrature IF LO tone from only one VCO. Based on an optimized frequency plan, it uses fewest nonlinear components like divide-by-N and mixer to suppress unwanted spurious tones. Its measured in-band sideband suppression ratio is more than 30 dBc for three sub-bands and it consumes only 17.6 mA from a 1.8 V supply.

Fully integrated wideband power amplifier in GaN technology

A fully integrated wideband power amplifier (PA) has been developed by using gallium nitride (GaN) 0.25-p.m technology. The PA is designed with commercial GaN process, in a single-ended configuration, starting from on-chip in-out matching. This PA adopts the saturated architecture and achieves average drain efficiency of 43.8% from 2.0 GHz to 3.0 GHz with an average output power and gain of 38 dBm and 15.4 dB respectively.