Jae Ho Jung

Modeling and Design Methodology of High-Efficiency Class-F and Class-

In this paper, efficiency-limiting physical constraint effects imposed on the knee voltage, along with a variation of the optimum load resistance, are investigated for highly efficient Class-F and Class- amplifiers. First, for an accurate analysis and comparison, new current waveform models are identified, and a realistic approach incorporated using a nonzero knee voltage and voltage-dependent nonlinear capacitance is employed to derive the voltage waveforms of the amplifiers. An analysis is performed to show the efficiency, output power, power gain, and output power compression points for both modes. Using this knowledge, along with a complete performance comparison, we provide a direction for optimizing the amplifier design. The analytic results are further verified based on the measured results of 3.54-GHz Class-F and Class- amplifiers using a commercial 60-W peak-to-envelope power gallium-nitride device. The experimental results show that Class-F and Class- amplifiers operate at drain efficiencies of 69.9% and 69.4% at saturated output powers of 47.4 and 47.2 dBm, respectively. These remarkably similar performances have excellent agreement with the predicted analysis at our operational frequency.

{\hbox{F}}^{{\hbox{-}1}}

In this paper, an analysis of a power amplifier manipulated using a second harmonic (PA-2HM) is described using a remarkable correlation between the fundamental and second harmonic impedances. The output loading condition, made up of an optimum fundamental impedance mapped to the conditional second harmonic reactance, allows us to achieve a high-efficiency power amplifier (PA) with a simple output matching circuit. For the analysis, the output voltage and current waveforms are modeled in terms of their output loading in order to extend the output power and efficiency. Specific PA-2HM cases, inverse Class-F and Class-J modes, are analyzed using different second harmonic reactance conditions. The allowable second harmonic reactance for maintaining maximum efficiency has been found to be spread throughout a wide range. To justify the analysis, a harmonic load-pull simulation and measurement are conducted and compared with analysis results. For verification, a commercially available 60-W gallium-nitride (GaN) device was used for different types of PA (inverse Class-F and Class-J) with appropriate second harmonic impedance. In terms of the output power and drain efficiency, the measured results are in good agreement with not only computer-aided design simulations, but also with our analysis and load-pull results.

Power Amplifiers

This paper presents a new power amplifier architecture incorporating a multi-level envelope delta sigma modulation (EDSM) encoder together with a dynamic bias control method to improve the overall efficiency. The proposed transmitter was developed based on a 3-level encoding process for quantizing the non-constant envelope signal. Therefore, the power amplifier is always operated under only a two-state output power level (maximum and 6dB back-off levels), achieving high efficiency. To maintain this high efficiency at a 6dB back-off output level, a lower DC supply voltage is supplied from a dual supply network (DSN) assisted on a digital process block. Using the proposed efficiency enhancement method, we have designed and implemented a 2.6GHz high-efficiency Class-J power amplifier (PA) using a commercial 10W PEP GaN device and a simple dual supply network. The experimental results show that, if the 0.51dB power loss of the band pass filter is de-embedded, the proposed power amplifier delivers a drain efficiency (DE) of 59.8% and power added efficiency (PAE) of 55.6%, with a gain of 11.1dB at an average output power of 34.5 dBm, for a 10 MHz 3G LTE signal with a 8.5 dB peak-to-average power ratio (PAPR).

Analysis of High-Efficiency Power Amplifier Using Second Harmonic Manipulation: Inverse Class-F/J Amplifiers

In this paper, a high-efficiency envelope-tracking (ET) transmitter incorporating a novel efficiency-boosting function is proposed and implemented. An inverse Class-F power amplifier is utilized and optimized using the proposed output loading condition, which enhances its efficiency at the high probability region. This matching network can be conveniently implemented by controlling the nonlinear capacitance of the power transistor. For an accurate analysis, the output waveforms are modeled in terms of the nonlinear capacitance, and the efficiency and output power are subsequently analyzed and successfully optimized. For a high-efficiency envelope amplifier (EA), we propose a new EA utilizing a 2-bit switching stage in place of a 1-bit switching stage. This proposed architecture effectively reduces the ripple current, improving the efficiency of the EA. To verify our analysis, we have fully implemented a 3.54-GHz high-efficiency ET transmitter including a digital processing block. The experimental results show that the ET transmitter using a commercial 60-W peak-envelope-power GaN device operates at a drain efficiency of 44% and power-added efficiency of 39.6% with a gain of 10.1 dB at an average output power of 40 dBm for a 10-MHz third-generation long-term evolution signal with 8.5-dB peak-to-average power ratio. Using a digital pre-distortion function, the adjacent channel leakage ratio is less than -47.5 dBc.

60% high-efficiency 3G LTE power amplifier with three-level delta sigma modulation assisted by dual supply injection

In this paper, we have proposed the new loop circulator structure with high isolation for time division duplexing (TDD) mobile radio system such as the high speed portable internet service (WiBro) in Korea. It is the important factor to isolate between the transmit signal and the receive signal for TDD system, because the white noise generated by the transmitter affect the noise figure of receiver system during the receiving period. Therefore, new technique to increase the isolation of a circulator is presented as adding the two additional circulators to the antenna port and the receiver input port, respectively. Because a proposed structure has twice isolation value than that of the single circulator, it has advantage for a high power TDD system for which a RF switch can not be used. about 20dB, the thermal noise amplified by the high power RF amplifier can be injected to the receiver during the receiving period. Besides, high RF power signal is leaked by a circulator with low isolation during the transmitting period and the receiver can be damaged. Accordingly, an additional device for protecting the receiver is required. As above mentioned, the isolation of the time division duplexing radio system is very important to reduce the noise figure of receiver. In this paper, new technique to increase the isolation of a circulator is presented as adding the two additional circulators to the antenna port and the receiver input port. The strength of transmit signal leaked to a receiver is isolated by the isolation of two circulators, and the transmit signal reduced by the transmission loss of two circulators is radiated through the antenna. Therefore, the function of new loop circulator structure is identical to that of the conventional single circulator, but its isolation is twice than that of a single circulator.

High-Efficiency Envelope-Tracking Transmitter With Optimized Class-

A 1.5-bit 20-MHz bandwidth continuous-time delta-sigma modulator (CT-DSM), which is suitable for envelope pulse-width modulation (EPWM) transmitters, is presented. To compensate the process-voltage-temperature variation, a resistor calibration method is proposed. The proposed calibration scheme improves a signal-to-quantization-noise-ratio (SQNR) by 18%. The switched capacitor digital-to-analog converter (DAC) and tri-level output DAC are adopted to improve non-ideal effects and implement multi-level encoding, respectively. Over 44 dB SQNR has been achieved for all corner simulation condition with an oversampling ratio of 13.056 and 20-MHz of bandwidth. The power consumption of the modulator is 11.6 mW from the 1.08 V supply. 1.74% of error vector magnitude can be obtained for a 20 MHz LTE signal with a 9.7 dB peak-to-average power ratio.

{\hbox{F}}^{-1}

We present efficient simplified behavioral models for power amplifier(PA) and its digital predistorter(DPD). Even though the many promising models have been proposed, more rigorous derivation and improvements in terms of performance and complexity are needed. In this paper, new approach is attempted to tackle the above. After building basis set based on simple rules, the new efficient and simplified models are derived by adding only the appropriate basis into the previous composite bases. The experimental results show that the proposed models for the PA and DPD outperform the conventional models.

Amplifier and 2-bit Envelope Amplifier for 3G LTE Base Station

This paper presents a 1.5 bit (3-level) envelope amplifier to improve the overall efficiency of wideband high linearity envelope tracking power amplifier. The proposed envelope amplifier has been devised with two switches providing the different supply voltages. Since the unnecessary current (ripple current) induced by a switching stage can be reduced by the multi-level quantization, the efficiency of a proposed envelope amplifier is 5% higher compared with that of a conventional architecture. With the proposed envelope amplifier, we have designed and implemented the 3.54GHz high efficiency envelope tracking power amplifier using a commercial 60W PEP GaN device. The efficiency boosting effect is further verified by the measured results. The experiment results show that the envelope tracking power amplifier operates at drain efficiency (DE) of 43.6% and power added efficiency (PAE) of 39.2% and a gain of 10.1dB at average output power of 40 dBm for a 10MHz WiMAX signal with 8.5 dB peak-to-average power ratio (PAPR). By using digital predistortion function, the adjacent channel leakage ratio (ACLR) is less than −45.4dBc at 20MHz offset.

New circulator structure with high isolation for time division duplexing radio systems

An advanced Class-S transmitter based on a tri-level delta-sigma modulator (DSM) is presented. The second order DSM shows a signal-to-noise and distortion ratio (SNDR) of 44.7 dB and a spurious-free dynamic range (SFDR) of 63.6 dB with a 3.1-MHz sinusoidal input at 522.24-MS/s using an offset cancellation scheme. The proposed technique improves the SFDR and SNDR over 10 dB and 3 dB, respectively. The proposed scheme can effectively control the input referred offset voltage of the DSM, resulting in the improvement of spectrum efficiency. The power consumption of the modulator is 13.4 mW from a 1.2 V supply. Measurements with a mixer show that the proposed modulator modulates a 10-MHz long-term evolution signal which has an 8.5 dB peak-to-average ratio with 3.30 % error vector magnitude and 38.7 dB adjacent channel leakage ratio at 2.6 GHz.

20-MHz bandwidth continuous-time delta-sigma modulator for EPWM transmitter

A LC-VCO topology without a varactor device has been proposed. The oscillator includes a variable capacitance block for a frequency tuning. The block consists of two transistors and two capacitors. The LC-VCO has been fabricated in a 130-nm CMOS technology. The measured results show operation frequencies of 3.73GHz to 3.94GHz and a phase noise of 119.1 dBc/Hz at 1-MHz offset frequency. Power consumption is 5.9mA from a 1.2V supply.