Bongsub Song

A 0.18-/spl mu/m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

A 0.18-μm CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM technique, the dual-mode 10-PAM technique can reduce power dissipation by 62.5%. The transmitter including a pseudo random bit sequence (PRBS) generator, multiplexers, an encoder, and an output driver achieves 10-Gb/s data-rate with 235-mW power dissipation such that the figure of merit (FOM) of the transmitter part is 23.5 mW/(Gb/s). The receiver including a flash type analog-to-digital converter (ADC), a decoder, and output drivers achieves 10-Gb/s data-rate and 10-12 BER with 190-mW power dissipation such that FOM of the receiver part is 19 mW/(Gb/s). The proposed 10-PAM transceiver was implemented in a 0.18-μm standard CMOS technology with 0.3 × 0.8-mm2 active area.

High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. A prototype sensor comprising 640 × 480 pixels was fabricated with a 0.13- μm CMOS process. The results of experiments conducted indicate that the proposed ADC can achieve a conversion time of 6.4 μs at a main clock frequency of 62.5 MHz, which is 10.2 times faster than the conventional SS ADC. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). Further, the proposed circuit employs redundancy error correction logic to calibrate the error between the coarse and fine steps. The total power consumption is 72 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital). The figure of merit (FoM) of the proposed VGA CMOS image sensor is 2.01 [e- nJ].

A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13-µm CMOS Technology.

A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It consists of voltage-scaled pull-up and pull-down networks, instead of conventional current switching networks. Not employing a tail current source, the proposed 4-PAM driver achieves the higher output voltage swing and lower power dissipation than conventional 4-PAM drivers. As a result, the proposed 4-PAM transmitter implemented in a 0.13-μm CMOS process achieved 10-Gb/s data rate with only 13.5-mW power dissipation.

A VGA CMOS Image Sensor with 11-bit column parallel single-slope ADCs

In this paper, CMOS Image Sensor (CIS) for VGA is presented. It has 11-bit column parallel single-slope ADCs. Single slope ADC is suitable for column parallel ADC of CIS. This CIS is fabricated in 0.13μm CMOS process. Its pixel size is 2.25 × 2.25 μm2. Total chip area is 5×5 mm. Its analog power consumption is 42.9 mW and digital power consumption is 1.6 mW.

A fast AFC technique with self-calibration for fast-locking PLLs

A fast adaptive frequency calibration (AFC) technique with self-calibration for fast-locking phase-locked loops is presented with frequency-selecting switches. The proposed AFC directly calculates the proper switch states of the voltage-controlled oscillator (VCO). It requires only six clock cycles of the reference oscillator regardless of the number of VCO switches to reach the final switch state in the ideal case. The proposed method counts the number of VCO cycles per reference clock period for the minimum VCO frequency (MIN) and the maximum VCO frequency (MAX) during the first four-clock periods. For the following two-clock periods, the proper states of the VCO switches are set to the calculated value from MIN, MAX and the desired division ratio for a target frequency (EST). A frequency synthesiser with the proposed AFC was implemented on a 0.18 µm CMOS process. The AFC time decreased from 40 to 0.4 µs employing the proposed scheme such that the total lock time is 40 µs with the loop bandwidth of 40 kHz.

A behavioural modelling of nonlinear RF power amplifiers using noise compensation technique

A nonlinear behavioural model of power amplifiers is proposed with an improved modelling method to fit up to the alternate channels where the noise contributions are dominant. From a memory polynomial model incorporating memory effects (Ku and Kenney 2003), noise contributions are considered for a better modelling. The proposed modelling method is utilised to model power amplifiers for Wideband Code Division Multiple Access (WCDMA) 1700 and 2100 bands. The power amplifier behaviour is modelled within 1 dB accuracy up to the alternate channels.

Improved Circuits for Single-photon Avalanche Photodiode Detectors

A CMOS photo detection bias quenching circuit is developed to be used with single photon avalanche photodiodes (SPADs) operating in Geiger mode for the detection of weak optical signals. The proposed bias quenching circuits for the performance improvement reduce the circuit size as well as improve the performance of the quenching operation. They are fabricated in a 0.18-㎛ standard CMOS technology to verify the effectiveness of this technique with the chip area of only 300 ㎛², which is about 60 % of the previous reported circuit. Two types of proposed circuits with resistive and capacitive load demonstrated improved performance of reduced quenching time. With a commercial APD by HAMAMATSU, the dead time can be adjusted as small as 50 ㎱.

An Autofocus Sensor With Global Shutter Using Offset-Free Frame Memory

An autofocus (AF) sensor with global shutters using offset-free frame memory is presented. A cross-shaped AF sensor array has left and right horizontal arrays and top and bottom vertical arrays. AF is achieved by calculating the phase difference from the digital code of the light illumination difference between the left and right (or top and bottom) arrays. The global shutter was implemented by using offset-free frame memories for accuracy enhancement. The proposed offset-free frame memories consist of flip-around sample-and-hold amplifiers with correlated double sampling. An active pixel sensor array, offset-free frame memories, a programmable gain amplifier, a 10-bit pipelined analog-to-digital converter, and digital control circuits are fully integrated on the chip fabricated on the 0.18-μm CMOS image sensor technology. It occupies 7 × 8 mm2 with bonding pads. Each active pixel size is 15 × 100 μm2. The total power consumption of the AF sensor is 660 mW at 3.3-V supply voltage.