Bonhoon Koo

Integrated Bias Circuits of RF CMOS Cascode Power Amplifier for Linearity Enhancement

This paper presents a highly linear differential cascode CMOS power amplifier (PA) with gate bias circuits in Common Source (CS) and Common Gate (CG) amplifiers. The proposed Class-D bias circuit at the gate of a CS amplifier injects a reshaped envelope signal only when the envelope signal is above a certain threshold voltage. This improves the linearity of the PA without significantly degrading the efficiency in a high-power region. In addition, the proposed bias circuit at the gate of a CG amplifier controls the second-order nonlinear components to improve the linearity and to reduce the sideband (IMD or ACLR) asymmetry, simultaneously. A single-stage PA including the bias circuits was fabricated using a 0.18-μ m CMOS process, with an integrated passive device (IPD) transmission line transformer (TLT). With a 3.5 V supply, the measurements show that 26.8 dBm with 43.3% PAE at -37 dBc ACLR (5 MHz offset) and 27.8 dBm with 45.8% PAE at -33 dBc ACLR (5 MHz offset) at 1.85 GHz under 3GPP WCDMA test without digital pre-distortions.

A fully integrated dual-mode CMOS power amplifier for WCDMA applications

Integrating a CMOS RF power amplifier (PA) into a single-chip transceiver is one of the most challenging works in implementing radio front-ends, which presents many advantages in handheld applications. Especially, low-power efficiency enhancement (LPEE) techniques, considering the probability distribution function of the practical wireless communication environments, extend the battery lifetime in handheld devices. Therefore, there are many studies for the LPEE in handheld CMOS PAs using transmission-line transformers (TLTs) with parallel amplifiers. Designing a series/parallel-combining transformer (SCT/PCT) is one of the key factors in the implementation of a dual-mode CMOS PA. However, the dual-mode performances of the PA must be optimized by using one output TLT structure. It is expected that there are difficulties in designing a highly efficient dual-mode PA. Therefore, this paper introduces a fully integrated dual-mode CMOS PA with a proposed output TLT with 2 control switches, which allows an LPEE with a back-off region of 10dB or more with a very low quiescent current.

A WLAN RF CMOS PA With Large-Signal MGTR Method

A CMOS linear power amplifier for wireless local area network IEEE 802.11b/g application is presented. To achieve high linear output power and high efficiency, a large-signal multigated transistor linearization method is proposed with an envelope injection gate bias circuit. A novel inter-stage matching transformer, which functions as a power splitter, is designed to implement this method. It is fabricated with a TSMC 0.13-μm standard RF CMOS process. Measurement shows 19.5-dBm Pout with 24.8% power-added efficiency (PAE) at - 25-dB error vector magnitude with an orthogonal frequency-division multiplexing 64-QAM 54-Mb/s 802.11g signal source and 23.15-dBm Pout with 31.73% PAE with DSSS, CCK, and 11-Mb/s 802.11b signal source without digital pre-distortion.

A CMOS Power Amplifier With a Built-In RF Predistorter for Handset Applications

A CMOS power amplifier (PA) with a built-in RF predistorter is proposed to improve the predistortion system efficiency, especially for handset applications. To eliminate the power consumption of an external predistorter and digital-to-analog converters in the control signal paths, the driver stage of the proposed PA has gain and phase control abilities according to two digital control words. This compensates for the distortions of the PA with envelope-dependent gain and phase control. It is implemented in a 0.18-μm RF CMOS process. The measurement results show 8.7 dB of gain control range and 49.4° of phase control range, which can compensate for the distortions of the designed PA. Using a WCDMA modulated signal, the PA improves its linear output power from 27.2 to 29.1 dBm and its linear efficiency from 34.8% to 41.1% by RF predistortion.

Highly efficient 24-GHz CMOS linear power amplifier with an adaptive bias circuit

A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (POUT) at a 1-dB-gain-compression-power (P1dB) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.

A dual-mode RF CMOS power amplifier with nonlinear capacitance compensation

A fully integrated dual-mode CMOS power amplifier (PA) with nonlinear MOS capacitance compensation is presented using 0.18-μm RF CMOS process. The proposed technique is used to implement dual mode structure as well as reduces AM-PM distortion. Dual-mode output matching network using transmission line transformer (TLT) is implemented for efficient dual mode operation. With a supply voltage 3.5V, the PA has the power gain of 26.2 and 14.2dB in low power mode (LPM) and high power mode (HPM), respectively. The quiescent current is only 28mA at LPM. The maximum linear output power satisfying 3GPP WCDMA modulated signal is 28/16.3dBm with a PAE 33.8/10.2% in the HPM/LPM.

RF CMOS Power Amplifiers for Mobile Terminals

Recent progress in development of CMOS power amplifiers for mobile terminals is reviewed, focusing first on switching mode power amplifiers, which are used for transmitters with constant envelope modulation and polar transmitters. Then, various transmission line transformers are evaluated. Finally, linear power amplifiers, and linearization techniques, are discussed. Although CMOS devices are less linear than other devices, additional functions can be easily integrated with CMOS power amplifiers in the same IC. Therefore, CMOS power amplifiers are expected to have potential applications after various linearity and efficiency enhancement techniques are used.

Linearization of RF CMOS power amplifiers

This paper presents two kinds of linearization techniques for RF CMOS Power Amplifiers (PAs). One is the linearization technique using adaptively controlled biases of Common Source (CS) and Common Gate (CG) amplifier in a cascode structure The ethers are the power-cell linearization techniques such as large signal multi-gated transistor (LS-MGTR) of a CS amplifier and adaptive power cell (APC) of CG amplifier.

Linearization methods of RF CMOS PAs for mobile communications

Although a CMOS device has inferior characteristics for PA it allows versatile controls and possible integrations with other circuits. These advantages surely provide us various methods to linearize a PA with resultant high efficiency. Several linearization methods of RF CMOS PAs are introduced in this paper. These are mostly based on adaptively controlling the biases of common source and common gate power transistors with the input envelope in many different manners. The other type effort is shown for a power driver linearizer which is made of a digital vector modulator. As examples, RF CMOS PAs for WCDMA and WLAN are demonstrated.

A 28-dBm pHEMT Power Amplifier Using Voltage Combiner for K-Band Applications

A K-band power amplifier was implemented using a 0.25-mum pHEMT process. A tournament-shaped voltage combiner that combines power by combining voltage was used in the output matching network. The voltage combining method alleviates the drain voltage swing requirement of the power transistor, whose junction breakdown voltage becomes quite low especially for high frequency applications. The chip size of the designed power amplifier is only 2.52 mm2. The amplifier achieved a P1dB of 28.0 dBm. The measured linear gain was 25 dB at 23.1 GHz. These demonstrate the operation of the tournament-shaped voltage combiner at K-band.