Changkun Park

A fully-integrated 900-MHz CMOS power amplifier for mobile RFID reader applications

A 900-MHz linear power amplifier has been fabricated for ultra-high-frequency (UHF) radio frequency identification (RFID) reader applications using a 0.25-mum CMOS technology. An on-chip transmission-line transformer is used for output matching network. Input and inter-stage matching components, and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier provides linear output power of 27 dBm at 920 MHz with a 2.5-V supply. Power-added-efficiency (PAE) at 1-dB-gain-compression point (P1dB) is 28 %. Gain flatness over the full UHF RFID band, which covers from 860 MHz to 960 MHz, is 1 dB

A High Dynamic Range CMOS RF Power Amplifier with a Switchable Transformer for Polar Transmitters

A fully integrated CMOS RF power amplifier for a 1.8 GHz band EDGE polar transmitter is presented. It is implemented with 0.18-mum CMOS process. The output power is 33.4 ~ 33.5 dBm and the power added efficiency is 39 ~ 41 percent when the frequency varies from 1.71 to 1.91 GHz. The dynamic range is increased by 12 dB with the use of the proposed switchable transformer, which meets the EDGE dynamic range requirement of 37 dB when the supply voltage changes from 0.8 to 3.3 V.

Properties of RFLDMOS with low resistive substrate for handset power applications

High performance lateral diffused MOSFETs on a CMOS platform have been developed for handset power applications. The LDMOS, with 0.3 /spl mu/m physical gate length and 7 nm gate oxide, shows high f/sub T/ and f/sub Max/ values up to 32 and 26 GHz, respectively, as well as low on-resistance of 3.1 ohm-mm and high saturated current of about 450 /spl mu/A//spl mu/m. The breakdown voltage is measured to be 14 V. More than 70% efficiency at 900 MHz is demonstrated in a unit power cell with a gate width of 1.92 mm.

1.8-GHz CMOS Power Amplifier with Stage-Convertible Structure Using Differential Line Inductor

A 1.8 GHz power amplifier for a polar transmitter application is implemented with 0.18 mum RF CMOS technology, and a differential line inductor is proposed for the differential circuit. The differential line inductor is used as a low power matching network in the stage-convertible power amplifier in order to increase the efficiency of a low output power region. The power amplifier achieved a power-added efficiency of 41% at a maximum output power of 31.5 dBm. The low power efficiency improvement for the power amplifier is 81% at an output power of 20 dBm.

Ku-band low noise amplifier with using short-stub ESD protection

A Ku-band ESD-protected low noise amplifier is designed using 0.15um pHEMT process. The input ESD protection is implemented with short-circuited stub. Since a short-circuited stub is used as an ESD protection as well as a matching element, there are no additional components and parasitic components associated with ESD protection. This endures 4400V (ESD tester limit) HBM test signal. The LNA has the noise figure of 1.24 dB and 24.5 dB gain at the frequency of 11.7-12.75 GHz.A Ku-band ESD-protected low noise amplifier is designed using 0.15um pHEMT process. The input ESD protection is implemented with short-circuited stub. Since a short-circuited stub is used as an ESD protection as well as a matching element, there are no additional components and parasitic components associated with ESD protection. This endures 4400V (ESD tester limit) HBM test signal. The LNA has the noise figure of 1.24 dB and 24.5 dB gain at the frequency of 11.7-12.75 GHz.

A CMOS power amplifier for a UHF RFID reader

A CMOS power amplifier for an RFID reader, which is implemented in a 0.18 mum CMOS process, is designed on a system IC, including output matching circuits. The developed amplifier has an efficiency of 27 % at 900 MHz and an output power of 24 dBm with a supply voltage of 1.8 V. In addition, it is isolated with shielding metal lines and is ESD protected. Furthermore, it is robust to high supply voltages and load impedance variations.

A 2.4-GHz HBT power amplifier using an on-chip transformer as an output matching network

A power Amplifier operating at 2.4-GHz is implemented using InGaP/GaAs HBT. The output matching network of the power amplifier is implemented on chip using 2:1 transformer. The transformer has less loss and broad frequency bandwidth in comparison with conventional LC output matching networks. Since a differential power cell is used, the power amplifier gets high gain although a sufficient ballast resistor is introduced. The measured input and output return losses are lower than −10 dB from 2.15 to 3-GHz. The center frequency of the small signal gain is 2.4-GHz, and the 1 dB bandwidth is 0.25-GHz. For 2.4-GHz input signal, power added efficiency at 1 dB compressed output power of 28.3 dBm is 40.2 %. The small signal gain is 29.8 dB. We can achieve a power and a gain matching in the same frequency range by using transformer as an output matching network.

Quad-band inverse class-F power amplifier using novel composite right/left-handed transmission line

In this paper, a quad-band inverse class-F power amplifier using the novel composite right/left-handed (CRLH) transmission lines (TLs) is developing covering 700 MHz, 800 MHz, 1800 MHz, and 2140 MHz. The novel CRLH TL metamaterials with two left-handed (LH) (backward) and two right-handed (RH) (forward) pass bands are used for quad-band operation. The second- and third-harmonics for four bands are located on open and short impedances for high-efficiency inverse class-F power amplifier. With the inverse class-F output matching network based on the quad-band harmonic control circuits, the measured maximum power-added efficiency (PAE) of the proposed quad-band inverse class-F power amplifier is 58.2 %, 50.3 %, 48.6 %, and 56.6 % for an output power of 41.5 dBm, 39.7 dBm, 37.7 dBm, and 40.7 dBm at 700 MHz, 800 MHz, 1800 MHz, and 2140 MHz, respectively.

A 28-dBm pHEMT Power Amplifier Using Voltage Combiner for K-Band Applications

A K-band power amplifier was implemented using a 0.25-mum pHEMT process. A tournament-shaped voltage combiner that combines power by combining voltage was used in the output matching network. The voltage combining method alleviates the drain voltage swing requirement of the power transistor, whose junction breakdown voltage becomes quite low especially for high frequency applications. The chip size of the designed power amplifier is only 2.52 mm2. The amplifier achieved a P1dB of 28.0 dBm. The measured linear gain was 25 dB at 23.1 GHz. These demonstrate the operation of the tournament-shaped voltage combiner at K-band.

On-chip power combining method in CMOS power amplifier

In this study, transformers were proposed to remove the degradation of the efficiency improvement in the low output power region. And a proposed tournament-shaped transformer, which is new architecture of magnetically coupled power combiner, is introduced and its advantages are presented.