Bonnie E. Weir

A study of soft and hard breakdown - Part I: Analysis of statistical percolation conductance

A theory of the statistical origin of soft and hard breakdown, that can explain a wide range of experimental data, is proposed. The theory is based on the simple premise that the severity of breakdown depends on the magnitude of the power dissipation through the sample-specific, statistically distributed percolation conductance, rather than on any physical difference between the traps involved. This model (a) establishes the connection between the statistical distribution of the theoretically predicted percolation conductance and the distribution of experimentally measured conductances after soft breakdown (Part I), and (b) explains the thickness, voltage, stress, and circuit configuration dependence of soft and hard breakdown (Part II). Connections to previous theories are made explicit, and contradictions to alternate models are resolved.

A study of soft and hard breakdown - Part II: Principles of area, thickness, and voltage scaling

For Part I see ibid., vol.49, no.2, pp.232-8 (2002). Based on the theory of soft and hard breakdown established in Part I of this paper, we now study the principles of area, thickness, voltage, and circuit configuration dependence of hard and soft breakdown. These scaling principles allow us to conclude that breakdown in ultrathin oxides stressed at operating voltages (1.0-1.5 V) can never be hard, which should allow a more relaxed reliability specification for these oxides.

Thin dielectric films: Uncorrelated breakdown of integrated circuits

In thick dielectrics, electrical breakdown is caused by the generation of spatially and temporally correlated defects that are produced — as in lightning — by feedback between defect formation and local stress. New defects are created in the vicinity of existing defects, leading to rapid and correlated propagation of field-induced defect chains that cause breakdown. By contrast, we show here that defects formed in ultrathin films subjected to realistic electrical stress remain spatially and temporally uncorrelated, even when multiple shorts (chains of defects) begin to bridge the thickness of the films. Besides their relevance to different applications of thin dielectric films, our results have positive implications for the scalability of modern integrated circuits.

Explanation of soft and hard breakdown and its consequences for area scaling

A simple theory of soft breakdown, that can explain wide ranging experimental data, is proposed. In addition, this model identifies the appropriate conditions for which soft breakdown turns into hard breakdown and the origin of bimodal failure distribution. Connections to older theories for thicker oxides are established and consequences of the new theory for the reliability of ultra-thin gate oxides are analyzed.

Statistically independent soft breakdowns redefine oxide reliability specifications

The statistics of soft-breakdown events in ultrathin oxide transistors are studied. By using new theoretical techniques and quantitative analysis, we demonstrate that spatial and temporal correlations among the successive breakdown events are weak. This allows us to redefine the standard specification of oxide reliability and suggest that ultrathin oxides will be far more reliable and fault-tolerant than has been assumed thus far.

An anode hole injection percolation model for oxide breakdown-the "doom's day" scenario revisited

A comprehensive percolation model is used to explore the role of non-uniform trap generation process on oxide breakdown. We show that this non-uniform trap generation (due to SILC and roughness induced localization) makes interpretation of experimental data difficult and can lead to incorrect projections for reliability of ultra-thin oxides.

Gate dielectric breakdown: A focus on ESD protection

The challenge of electrostatic discharge (ESD) design is that as scaling continues and operating voltages are lowered, the interface to the outside world and therefore the ESD specifications remain the same. Moreover, as has been highlighted by Duvvury et al. (1996), the first breakdown voltage for snapback of a transistor and the median breakdown voltage of the gate dielectric are converging, making it difficult to ensure the robustness of gate dielectrics in an ESD event. This is particularly true for 1V I/Os in high-speed, high-performance applications, where transistor gates may be directly connected to an external pin or NFETs may be used as compact decoupling capacitors between VDD and VSS, exposing the thin gate dielectric to ESD stress. The ESD protection and interconnects can both contribute voltage drops during an ESD pulse, and their sum must not be higher than the voltage which a dielectric can withstand. Especially alarming is the fact that in the sub-2nm regime, significant statistical variation exists as well as a dependence on area for dielectric breakdown. A vast knowledge base exists for oxide breakdown in the long time-scale, and a few publications have addressed short time-scales. For the most part, studies which described breakdowns at short times have used methodology developed for thicker oxides. In the case of thinner oxides or oxynitrides, the voltage acceleration is no longer 1/E, the dielectric breakdown voltage depends sensitively on the dielectric area, and small differences in thickness have a significant effect on the dielectric breakdown voltage. Therefore, the purpose of this paper is to study the relevance of long time-scale TDDB data in predicting the response to short time-scale ESD events, especially for sub-2nm dielectrics in both NFETS and PFETS.

A computational model for oxide breakdown: theory and experiments

The present status of computational models for oxide reliability and their success in interpreting the experimental data are reviewed. We find that significant progress has been made in theoretical modeling of all aspects of reliability, and this understanding of the underlying degradation mechanism allows continued oxide scaling beyond the limits previously assumed possible.

Gate dielectric breakdown in the time-scale of ESD events

Abstract Transmission line pulse (TLP) measurements are used to demonstrate that oxynitride breakdown projections from DC measurements using conventional area and voltage-scaling techniques can be extended to the nanosecond time-scale. ESD protection systems can thus be designed to prevent dielectric breakdown. Important concepts in gate dielectric breakdown such as the anode–hole injection model and area and statistical effects are discussed and applied to the nanosecond regime.

Soft breakdown at all positions along the N-MOSFET

Abstract We observe soft breakdowns at all positions along the gates of N-MOSFETs when testing is performed at low voltage or with low current compliance. Devices whose breakdown spots are at or near the gate–drain overlap region have the highest off-currents, although not high enough to be fatal to device operation.