Dhanoop Varghese

on-State Hot Carrier Degradation in Drain-Extended NMOS Transistors

A close analysis of the universality of OFF-state hot carrier degradation (HCI) in drain-extended transistors suggests that on-state HCI degradation should likewise be universal. In this paper, we confirm this hypothesis through an extensive set of experiments on drain-extended n-channel metal-oxide-semiconductor (DeNMOS) transistors and demonstrate that the underlying mechanism for both OFF- and ON-state degradation are essentially identical (even though the drain current differs by several orders of magnitude for the respective stress bias conditions). We show how this universality of ON- and OFF-state hot carrier degradations allows the use of short-term measurements to predict device lifetime under arbitrary operating conditions.

OFF-state degradation and correlated gate dielectric breakdown in high voltage drain extended transistors: A review

Abstract High voltage transistors exhibit unique degradation modes that cannot always be explained based on classical degradation mechanisms. In this paper, we use the specific example of OFF-state degradation in high voltage drain extended transistors to develop a generalized degradation model that can be extended to a wide range of device geometries (DeMOS, LDMOS, CMOS) and bias conditions (OFF-state, sub-threshold, ON-state). We show that hot carriers generated from impact ionization of leakage current components are responsible for OFF-state degradation by breaking interfacial and bulk Si O bonds. The resultant degradation is shown to be universal and the kinetics of Si O bond breaking is explained based on a bond-dispersion model. The generalized “bottom-up” model also explains the correlated gate dielectric breakdown and higher Weibull slopes at OFF-state conditions which are not anticipated based on classical hot carrier models. Our approach unifies hot carrier degradation results from various laboratories across the world within a common conceptual framework.

The Role of Dielectric Heating and Effects of Ambient Humidity in the Electrical Breakdown of Polymer Dielectrics

Polymer-based dielectric materials have potential applications in microelectronics, power electronics, photovoltaics, flexible electronics, MEMS, and sensing industries. The possibility of premature electrical breakdown due to high electric fields, particularly at high frequencies and in high ambient temperature and humidity conditions, has restricted its widespread adoption. In this paper, we generalize the thermochemical model of dielectric breakdown and establish dielectric heating as the primary ac degradation mechanism in polymers and develop an analytical dielectric breakdown model that satisfactorily explains measured trends in constant and ramp stress tests under both ac and dc electric fields applied to 5-μm-thick PBO capacitors. We also study and quantify the effects of exposure to ambient relative humidity on the electrical breakdown lifetime of polymer dielectrics. Our study provides a fundamental physical understanding of the frequency, ambient humidity, and thickness dependencies of lifetime and breakdown strength for polymer dielectrics; the proposed breakdown model suggests far more optimistic dielectric lifetimes when accelerated test results are scaled to normal operating conditions.

Role of encapsulation formulation on charge transport phenomena and HV device instability

Four molding-compound composites with different silica micro-filler size and concentration have been measured on top of dedicated IC test structures. The leakage current of charge sensors has been monitored under different high-voltage stress during charging/discharging transients occurring in the mold. Physical insight of space charge distribution at high electric field and temperature has been obtained by TCAD analysis. The role played by the encapsulation composition on the device-package interaction has been investigated via TCAD simulations of the HTRB test of a Single-RESURF LDMOS.

Observation and Control of Hot Atom Damage in Ferroelectric Devices

Ferroelectric materials are the most common example of a Landau structure, defined as a system having an atom/mass moving in a double-well energy landscape. These materials have applications in memories, actuators, low power logic transistors, and so on. For a bipolar ac signal typical in most of the applications, one suspects that the repeated roller coaster shuttling of the moving atoms located microscopically at the domain walls could lead to bond dissociation, suggesting a new channel for defect generation with no classical counterpart. Here, we demonstrate that once the bipolar pulses initiate transfer of atoms between the energy pockets, the transient overshoot away from their equilibrium positions (hot atoms) leads to significant increase in defect generation. We interpret the degradation theoretically and demonstrate a set of soft-switching schemes to control the hot atom damage and to improve the device lifetime dramatically. The damage mechanism should be generic in other Landau structures, such as microelectromechanical systems, nonvolatile memories, and analogous control strategies should improve the lifetime of all such bistable devices.

Sub-threshold current based acceleration and modeling of OFF-state TDDB in drain extended NMOS and PMOS transistors

It is not always practical to observe OFF-state drain-to-gate dielectric breakdown in power transistors due to the upper limit set to stress voltage by junction breakdown. In this paper we demonstrate that OFF-state breakdown in drain extended power transistors can be accelerated by increasing the channel current (IS) by biasing the transistor in sub-threshold. We also show that the charge pumping scaling factors along with observed breakdown times can be used to build an IS and VDG dependent model to extrapolate failure times at operating bias conditions.

Energy driven modeling of OFF-state and sub-threshold degradation in scaled NMOS transistors

We study OFF-state and sub-threshold degradation in scaled NMOS transistors and propose a unified channel current (IS) and drain-to-source voltage (VDS) dependent lifetime model for a wide range of bias conditions. The lifetime dependence on VDS suggests that degradation is limited by the maximum energy available for the channel electron in short channel transistors.

Electrical characterization of epoxy-based molding compounds for next generation HV ICs in presence of moisture

Abstract The effects of moisture on the electrical properties of epoxy molding compounds containing high quantities of silica filler microparticles have been investigated by means of dielectric spectroscopy, steady-state conductivity and pulsed electro-acoustic space charge measurements. It has been shown that the presence of water at the filler/epoxy interfacial areas affects the low-frequency dielectric response of the materials and significantly increases their electrical conductivity, especially at higher temperatures. In addition, in presence of moisture, space charge measurements have shown the accumulation of heterocharges which significantly increase the electric field at the electrodes. These aspects are of primary importance, as the electrical properties of the encapsulation materials strongly influence the space charge distribution in high voltage devices.

Role of the Insulating Fillers in the Encapsulation Material on the Lateral Charge Spreading in HV-ICs

High electric fields and temperatures in high-voltage ICs (HV-ICs) can induce charge transport phenomena in the encapsulation material leading to reliability test failures. In this paper, the resistivity of epoxy-based resins with insulating microfiller weight fraction exceeding 70% has been experimentally and theoretically investigated for the first time. Electrical conductivity has been measured at high temperature (150 °C) using both dielectric spectroscopy analysis on bulk samples and charge-spreading characterizations on a dedicated test chip with integrated charge sensors. The use of a charge sensor close to the internal HV metallization leads to results more pertinent with the active area of HV-ICs. Remarkably, both experiments show an unexpected increase and a significant variability of the electrical conductivity as the microfiller fraction is increased. The strong correlation between bulk and lateral experiments clearly indicates that those features should be attributed to the bulk material. Numerical simulations of diffusion phenomenon in mold structures with random arrangements of spherical microfillers demonstrate that the conductivity increase with filler content can be ascribed to the role of the epoxy/filler interfaces.

TCAD analysis of HCS degradation in LDMOS devices under AC stress conditions

Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isolation (STI). The HCS degradation curves have been measured on wafer by varying frequency and duty-cycle under a high-VDS stress for both low and high Vgs biases. The linear drain current drifts have been also investigated through TCAD predictions under AC stress conditions for the first time. A quantitative explanation of the dependence on frequency and duty cycle has been obtained using the new approach based on physical models. An extended analysis of the HCS degradation in a real switching application through a resistive load has been reported to gain an insight on the role played by the peak-HCS rates during the rising/falling edges.