Boris Habets

Non-linear methods for overlay control

Overlay requirements for DRAM devices are decreasing faster than anticipated. With current methods overlay becomes ever harder to control and therefore novel techniques are needed. This paper will present an alignment based method to address this issue. The use and impact of several non-linear alignment models will be presented. Issues here include the number of alignment marks to use and how to distribute them over the wafer in order to minimize the throughput impact while at the same time providing maximum wafer coverage. Integrating this method into a R2R environment strongly depends on the stability of the process. Advantages and disadvantages of the method will be presented as well as experimental results. Finally some comments will be given on the need and feasibility of wafer by wafer corrections.

Understanding overlay signatures using machine learning on non-lithography context information

Overlay errors between two layers can be caused by non-lithography processes. While these errors can be compensated by the run-to-run system, such process and tool signatures are not always stable. In order to monitor the impact of non-lithography context on overlay at regular intervals, a systematic approach is needed. Using various machine learning techniques, significant context parameters that relate to deviating overlay signatures are automatically identified. Once the most influential context parameters are found, a run-to-run simulation is performed to see how much improvement can be obtained. The resulting analysis shows good potential for reducing the influence of hidden context parameters on overlay performance. Non-lithographic contexts are significant contributors, and their automatic detection and classification will enable the overlay roadmap, given the corresponding control capabilities.

In-depth analysis and characterization of a dual damascene process with respect to different CD

In a 200 mm high volume environment, we studied data from a dual damascene process. Dual damascene is a combination of lithography, etch and CMP that is used to create copper lines and contacts in one single step. During these process steps, different metal CD are measured by different measurement methods. In this study, we analyze the key numbers of the different measurements after different process steps and develop simple models to predict the electrical behavior* . In addition, radial profiles have been analyzed of both inline measurement parameters and electrical parameters. A matching method was developed based on inline and electrical data. Finally, correlation analysis for radial signatures is presented that can be used to predict excursions in electrical signatures.

Geometry-based across wafer process control in a dual damascene scenario

Dual damascene is an established patterning process for back-end-of-line to generate copper interconnects and lines. One of the critical output parameters is the electrical resistance of the metal lines. In our 200 mm line, this is currently being controlled by a feed-forward control from the etch process to the final step in the CMP process. In this paper, we investigate the impact of alternative feed-forward control using a calibrated physical model that estimates the impact on electrical resistance of the metal lines* . This is done by simulation on a large set of wafers. Three different approaches are evaluated, one of which uses different feed-forward settings for different radial zones in the CMP process.

Higher order intra-field alignment for intra-wafer lens and reticle heating control

Before each wafer exposure, the photo lithography scanner’s alignment system measures alignment marks to correct for placement errors and wafer deformation. To minimize throughput impact, the number of alignment measurements is limited. Usually, the wafer alignment does not correct for intrafield effects. However, after calibration of lens and reticle heating, residual heating effects remain. A set of wafers is exposed with special reticles containing many alignment marks, enabling intra-field alignment. Reticles with a dense alignment layout have been used, with different defined intra-field bias. In addition, overlay simulations are performed with dedicated higher order intra-field overlay models to compensate for wafer-to-wafer and across-wafer heating.

Advanced combined overlay and CD uniformity measurement mark for double patterning

Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.

In-depth analysis of indirect overlay method and applying in production environment

Overlay measurements are done for verification of the exposure and creation of process corrections for the next lots. As throughput of the overlay measurement tools is limited, it is desirable to avoid unnecessary measurements. Another concern can be that in-transparent stacks do not allow measuring a critical overlay relation directly. We developed methods for calculation of the overlay relation between two different layers between which there is no direct overlay measurement. We qualify the impact of sampling plans and the number of dependent layers. The indirect overlay calculation is applied on a significant high volume data set.

Topography based wafer clustering for wafer level overlay correction

Non-linear overlay deformation is a well-known problem in critical lithography steps. A significant root cause is nonuniform stress, often caused by high temperature processes. Non-uniform stress in the wafer causes vertical deformation of the wafer, which can be measured by topography measurement equipment. In this case study, clustering is done on the topography data to sort each wafer into groups. Using the context information from the clustering, overlay feedback is computed on a wafer level basis. The evaluation of the approach is done with a run-to-run simulation, which allows optimization of this method and evaluation of the on-product overlay performance improvement. In the analysis, different wafer zones are distinguished to characterize the improvement potential for the different zones.

Monitoring of multi-patterning processes in production environment

Multi-patterning processes have become common in the leading-edge semiconductor industry. These processes require a good patterning uniformity over the wafer while different process steps have impact. The initial lithography steps can be nearly perfect, but the CD variation after a trim process may cause CD variation after the spacer deposition. In fact, that leads to final non-uniformity of the final CD. Monitoring and controlling the individual CD parameters is not sufficient to ensure a stable process. We define a set of new KPIs, taking all contributions into account and using macro measurement data. We show that a reliable monitoring is achieved to meet the process specifications.

Combined process window monitoring for critical features

After critical lithography steps, overlay and CD are measured to determine if the wafers need to be re-worked. Traditionally, overlay metrics are applied per X/Y-direction and, a CD metric is computed independently. From design standpoint, electrical failure is based on a complex interaction between CD deviations and overlay errors. We propose a method including design constraints, where results of different measurement steps are not judged individually, but in a combined way. We illustrate this with a critical design feature consisting of a contact requiring minimum distance to a neighboring metal line, resulting in much better correlation to yield than traditional methods.