Boris Hudec

High-permittivity metal-insulator-metal capacitors with TiO2 rutile dielectric and RuO2 bottom electrode

We describe properties of MIM capacitor structures with the RuO2 bottom electrode, TiO2 dielectric film and various top electrodes. The TiO2 films were grown by atomic layer deposition (ALD) at temperature 425 °C on metal organic chemical vapour deposited (MOCVD) RuO2 bottom electrodes grown at 300 °C. Due to local epitaxial growth on the RuO2 rutile structure, TiO2 films with the permittivity 135 and equivalent oxide thickness 0.58 nm were obtained. Capacitance density as high as 60 fF/μm2 was achieved. Au and Ni films for top electrodes were prepared by evaporation at room temperature. RuO2 films for top electrodes were grown by MOCVD. Strong effect of top electrode material on capacitance and leakage currents was observed. In addition, the stacks with TiO2 dielectric were found to be very sensitive to oxygen post-deposition treatment.

Impact of plasma treatment on electrical properties of TiO2/RuO2 based DRAM capacitor

In this work, we systematically studied the influence of the plasma treatment (PT) on the structural and electrical properties of Pt/rutile-TiO2/RuO2 metal–insulator–metal capacitors. The leakage current of the 12 nm thick TiO2 dielectrics prepared by atomic layer deposition was reduced below 10−7 A cm−2 while the capacitance equivalent thickness was kept below 0.5 nm using oxygen PT of the bottom RuO2 electrode. Reflection high energy electron diffraction, transmission electron microscopy, atomic force microscopy and x-ray photoelectron spectroscopy analyses allowed the conclusion that O2 plasma smoothened the RuO2 surface and increased its oxygen content through plasma induced surface reconstruction. The nucleation of TiO2 on the plasma-treated surface was faster while the thickness of the capacitor dead layer at the TiO2/RuO2 interface was reduced.

Atomic layer deposition grown metal-insulator-metal capacitors with RuO2 electrodes and Al-doped rutile TiO2 dielectric layer

Metal-insulator-metal structures for dynamic random access memory capacitor applications were prepared by atomic layer deposition. Rutile TiO2 dielectric layers were grown on top of RuO2 electrodes. TiO2 layers were doped in different ways by aluminum and these structures were compared to undoped ones. C-V and J-V measurements show that Al doping reduces the capacitance density of the stacks while reducing leakage current. Varying the initial Al doping profile did not change the electrical properties of the stacks. Leakage current analysis revealed that the current in the doped samples is controlled by Schottky emission.

Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication

Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.

3D resistive RAM cell design for high-density storage class memory—a review

In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes—3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.

Nanoscale Characterization of TiO2 Films Grown by Atomic Layer Deposition on RuO2 Electrodes

Topography and leakage current maps of TiO2 films grown by atomic layer deposition on RuO2 electrodes using either a TiCl4 or a Ti(O-i-C3H7)4 precursor were characterized at nanoscale by conductive atomic force microscopy (CAFM). For both films, the leakage current flows mainly through elevated grains and not along grain boundaries. The overall CAFM leakage current is larger and more localized for the TiCl4-based films (0.63 nm capacitance equivalent oxide thickness, CET) compared to the Ti(O-i-C3H7)4-based films (0.68 nm CET). Both films have a physical thickness of ∼20 nm. The nanoscale leakage currents are consistent with macroscopic leakage currents from capacitor structures and are correlated with grain characteristics observed by topography maps and transmission electron microscopy as well as with X-ray diffraction.

Interface engineered HfO2-based 3D vertical ReRAM

We demonstrate a double-layer 3D vertical resistive random access memory (ReRAM) stack implementing a Pt/HfO2/TiN memory cell. The HfO2 switching layer is grown by atomic layer deposition on the sidewall of a SiO2/TiN/SiO2/TiN/SiO2 multilayer pillar. A steep vertical profile was achieved using CMOS-compatible TiN dry etching. We employ in situ TiN bottom interface engineering by ozone, which results in (a) significant forming voltage reduction which allows for forming-free operation in AC pulsed mode, and (b) non-linearity tuning of low resistance state by current compliance during Set operation. The vertical ReRAM shows excellent read and write disturb immunity between vertically stacked cells, retention over 104 s and excellent switching stability at 400 K. Endurance of 107 write cycles was achieved using 100 ns wide AC pulses while fast switching speed using pulses of only 10 ns width is also demonstrated. The active switching region was evaluated to be located closer to the bottom interface which allows for the observed high endurance.

RuO 2 /TiO 2 based MIM capacitors for DRAM application

MIM capacitors with MOCVD-grown RuO<inf>2</inf> bottom electrode, ALD-grown TiO<inf>2</inf> rutile dielectric and RuO<inf>2</inf> and Pt top electrodes were prepared and characterised by the means of C-V and J-V measurements. Dielectric constants were in the range of 140, which correspond to EOT of 0.5 nm and leakage current density as low as 1.5*10⁻⁶ A/cm² was achieved. Strong influence of TiO<inf>2</inf> stoichiometry on the leakage currents was found and analysed.

Resistive switching in RuO 2 /TiO 2 /RuO 2 MIM structures for non-volatile memory application

In this paper we describe resistive switching in RuO<inf>2</inf>/TiO<inf>2</inf>/RuO<inf>2</inf> structures. Electrodes (RuO<inf>2</inf>) were grown by metal organic chemical vapor deposition and dielectric TiO<inf>2</inf> switching layers with rutile structure were prepared by atomic layer deposition. After proper nitrogen annealing of as-grown samples followed by an electro-forming procedure and forming procedure bipolar resistive switching was observed. For various switching parameters 100 switching cycles were performed to test retention characteristics. Ratio of high to low resistance up to 10³ was obtained for reading voltage of −0.3 V.

Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse

Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.