Tuo-Hung Hou

Electrode dependence of filament formation in HfO2 resistive-switching memory

This study investigates bipolar and nonpolar resistive-switching of HfO2 with various metal electrodes. Supported by convincing physical and electrical evidence, it is our contention that the composition of conducting filaments in HfO2 strongly depends upon the metal electrodes. Nonpolar resistive-switching with the Ni electrode is attributed to the migration of metal cations and the corresponding electrochemical metallization. Conversely, oxygen-deficient filaments induced by anion migration are responsible for bipolar resistive-switching. It was also found that the characteristic nature of the conducting filaments influences many aspects of switching characteristics, including the switching power, cycling variations, and retention at elevated temperatures.

Transition of stable rectification to resistive-switching in Ti/TiO2/Pt oxide diode

We have fabricated a Ti/TiO2/Pt oxide diode with excellent rectifying characteristics by the asymmetric Schottky barriers at the Ti/TiO2 (0.13 eV) and the TiO2/Pt (0.73 eV) interfaces. Instead of homogeneous conduction, the current transport is governed by the localized oxygen-deficient TiO2 filaments. In addition, the reproducible resistive-switching exists in the same structure, triggered by the forming process. The transition between two modes is ascribed to the destruction of the interface barriers at forming. The rectification stable up to 125 °C and 103 cycles under ±3 V sweep without interference with resistive-switching shows satisfactory reliability of TiO2 diodes for one diode-one resistor memory devices.

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process. it was found to gain additional /spl sim/10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process. which is a promising local strain approach for sub-65nm CMOS application.

Bipolar Nonlinear

A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO2/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO2 barriers. The series connection with an HfO2-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.

\hbox{Ni/TiO}_{2}\hbox{/}\hbox{Ni}

The three-dimensional (3D) electrostatics together with the modified Wentzel-Kramers-Brillouin tunneling model has been implemented to simulate the programming and retention characteristics of the metal nanocrystal (NC) memories. Good agreements with experimental data are first demonstrated to calibrate the transport parameters. In contrast to previous works, the 3D electrostatic effects investigated in this paper are proven very significant in the memory operations. Therefore, new design criteria of metal NC memories are investigated. Part I presents the physical model and the NC array design optimization. A sparse and large-size NC array, which is suitable for the one-dimensional narrow-channel memories, provides higher program/erase tunneling current density due to the field-enhancement effect and lower charging energy due to the large NC capacitance. On the other hand, to achieve a sufficient memory window, fast programming speed, and long retention time in the typical two-dimensional channel memories, a dense and large-size NC array is favorable while taking the tradeoff with the NC number density into account. Based on the same theoretical model, the authors continue in Part II to consider the design optimization when high-K dielectrics can be employed

Selector for 1S1R Crossbar Array Applications

Precise electrical manipulation of nanoscale defects such as vacancy nano-filaments is highly desired for the multi-level control of ReRAM. In this paper we present a systematic investigation on the pulse-train operation scheme for reliable multi-level control of conductive filament evolution. By applying the pulse-train scheme to a 3 bit per cell HfO2 ReRAM, the relative standard deviations of resistance levels are improved up to 80% compared to the single-pulse scheme. The observed exponential relationship between the saturated resistance and the pulse amplitude provides evidence for the gap-formation model of the filament-rupture process.

Design Optimization of Metal Nanocrystal Memory—Part I: Nanocrystal Array Engineering

Lack of a suitable selection device to suppress sneak current has impeded the development of 4F2 crossbar memory array utilizing stable and scalable bipolar resistive-switching. We report a high-performance nonlinear bipolar selector realized by a simple Ni/TiO2/Ni MIM structure with a high current density of 105 A/cm2, and a Ni/TiO2/Ni/HfO2/Pt vertically stacked 1S1R cell capable of gigabit memory implementation. Furthermore, the demonstration of 1S1R array fabricated completely at room temperature on a plastic substrate highlights the promise of future extremely low-cost flexible nonvolatile memory.

Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations.

A novel NiSi process with a thin Ti-cap layer is proposed, for the first time, to improve the leakage problem of Ni-silicided junction. The Ti-cap samples exhibit a very low leakage current density about 1/spl times/10/sup -9/ A/cm/sup 2/ after 600/spl deg/C annealing, which is one order of magnitude reduction comparing with uncapped samples. From Auger analyzes, it is found that this significant improvement results from suppression of the oxidation of the Ni-silicide during the thermal annealing process.

One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications

A two-terminal analog synaptic device that precisely emulates biological synaptic features is expected to be a critical component for future hardware-based neuromorphic computing. Typical synaptic devices based on filamentary resistive switching face severe limitations on the implementation of concurrent inhibitory and excitatory synapses with low conductance and state fluctuation. For overcoming these limitations, we propose a Ta/TaOx/TiO2/Ti device with superior analog synaptic features. A physical simulation based on the homogeneous (nonfilamentary) barrier modulation induced by oxygen ion migration accurately reproduces various DC and AC evolutions of synaptic states, including the spike-timing-dependent plasticity and paired-pulse facilitation. Furthermore, a physics-based compact model for facilitating circuit-level design is proposed on the basis of the general definition of memristor devices. This comprehensive experimental and theoretical study of the promising electronic synapse can facilitate realizing large-scale neuromorphic systems.

Improvement of junction leakage of nickel silicided junction by a Ti-capping layer

High-performance amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are successfully fabricated on a colorless polyimide substrate using a top-gate self-aligned structure. All thin films are deposited by roll-to-roll-compatible sputtering processes at room temperature. The maximum field-effect mobility is 18 cm2/V·s, the threshold voltage is -1.35 V, the subthreshold slope is 0.1 V/decade, and the on/off current ratio is about 105. The results highlight that excellent device performance can be realized in a-IGZO TFTs without compromising manufacturability.