Bosco Leung

Multibit Sigma - Delta A/D converter incorporating a novel class of dynamic element matching techniques

A dynamic element matching technique is applied to multibit sigma-delta modulators. The approach translates the harmonic distortion components of a nonideal digital-to-analog converter (DAC) in the feedback loop of a sigma-delta modulator to high-frequency components, which can then be filtered out by the decimation filter. Computer simulations have confirmed that with this approach a third-order sigma-delta modulator employing a 3-bit forward ADC, a 3-bit feedback DAC with a random mismatch of 0.1% can achieve a 104-dB (17+bit) dynamic range and a harmonic distortion below 100 dB, with an oversampling ratio of 64. The technique does not generate any tone in the passband. >

A high resolution multibit sigma-delta modulator with individual level averaging

A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 /spl mu/m CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 kHz baseband. No tone is observed in the baseband as the amplitude of a 10 kHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm/sup 2/ and it dissipates 67.5 mW of power from a 5 V supply. >

STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits

STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits that conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical circuit descriptions and a symbolic/numeric solve unit that dynamically integrates analytical model equations across hierarchical boundaries. The output of the solver is a flattened homogeneous model that is customized to a user-specified topology and set of performance specifications. The output is thus tailored for optimization and other numerically intense design exploration procedures. All model descriptions include physical layout so that important net parasitics may be fully accounted for during design evaluation. Synthesis proceeds via a successive solution refinement methodology. Multilevel models of increasing sophistication are used by scan and optimization modules to converge to what is likely a globally optimal solution. Design experiments have shown that STAIC can produce satisfactory results. >

A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input

The design of a passive sigma-delta modulator without using operational amplifiers is presented. Issues of its application to IF digitization with subsampling scheme are discussed. In addition, a switch-only gain-boost network is proposed to achieve a dc voltage gain in a passive way. The prototype chip of a second-order passive sigma-delta modulator was fabricated in a 1.2-/spl mu/m CMOS process. Testing results showed that with a 10-MHz IF input (bandwidth of 20 kHz), the modulator achieved a 13-b resolution at 0.25 mW with a 3.3 V power supply. Good performance was also measured with a baseband input.

Distortion analysis of MOS track-and-hold sampling mixers using time-varying Volterra series

A time-varying theory of Volterra series is developed and applied in the sampled-data domain to solve for harmonic and intermodulation distortion of a MOS-based track-and-hold sampling mixer with a nonzero fall-time LO waveform. Distortion due to sampling error is also calculated. These results, when combined with the continuous-time solution, quantify harmonic and intermodulation distortion of a track-and-hold type mixer completely. Closed form solutions are obtained. As a practical consequence, it is shown that for certain fall-time, the distortion of track-and-hold mixers can be better than what would be predicted by a simple application of time-invariant Volterra series theory.

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chips output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.

High-order single-stage single-bit oversampling A/D converter stabilized with local feedback loops

A new method for the stabilization of high-order (>2) single-stage single-bit oversampling A/D converters is proposed. In this approach, the stability of the modulator is achieved by preventing any unbounded increase in the internal node-voltages through the insertion of local feedback signals inside the modulator loop. In the past, absolute bounds for stability have been derived for the first-order converter. This property is exploited in stabilizing a higher order loop by activating local first-order loops as soon as the internal integrators overload. With local feedback, individual integrators are prevented from saturating and the output voltages are within the proper bounds. The error caused by the local feedback signals is cancelled by feeding these signals through alternate signal paths, in a way similar to the quantization noise cancellation mechanism in a MASH architecture. Since the frequency of overloading can be made very low by proper design, the effect of imperfect cancellation due to mismatches in the two signal paths caused by the modulator nonidealities is quite small. Hence, compared to the inherently stable MASH architectures, the proposed approach achieves stability and is yet much less sensitive to component mismatches. In a sampled data environment where the integrator is realized using op amps, this translates into a low op amp gain requirement. Simulation results confirm that third order modulators using op amps with gain as low as 50 achieve a peak signal-to-noise ratio (SNR) of about 83 dB with an oversampling ratio of 64. This is less than 1 dB from the SNR achieved with infinite op amp gain. >

The oversampling technique for analog to digital conversion: a tutorial overview

Oversampled technique has received wide attention in the VLSI implementation of analog to digital interface. The technique relies on the fundamental principle of trading off temporal resolution with amplitude resolution. This trade-off allows the ADC (Analog to Digital Converter) to achieve resolution beyond the limitations imposed by the matching tolerance of fine line VLSI technology. In addition it simplifies the overall system design by relaxing the front end anti-aliasing requirement.

A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop

A 0.8-/spl mu/ BiCMOS, 400-MHz intermediate-frequency digitizer based on embedding a down-conversion mixer inside a sigma-delta modulator together with a reconstruction filter in the feedback path has been developed. The digitizer, when subsampled with a clock of 20 MHz, achieves a measured resolution of 12 bits for a 40-kHz bandwidth and dissipates 18 mW of power. The third harmonic distortion (HD/sub 3/) is less than -90 dBc for a -4-dB input, and the third-order intermodulation product (IM/sub 3/) is less than -70 dBc for a -8-dB input, with a full-scale voltage of 0.5 V. The chip area is 1.5 mm/sup 2/.

BiCMOS current cell and switch for digital-to-analog converters

A BiCMOS current cell and current switch used in a current steering DAC are proposed. The BiCMOS self-calibrated current cell offers higher output resistance and smaller minimum voltage and shows up to a factor of 2 improvement in accuracy in simulations. The BiCMOS current switch has no base current error and achieves close to a factor of 2 improvement in simulated switching speed when compared to a MOS switch. >