Subhajit Sen

CMOS multi-phase switched capacitor step-up DC-DC converter

This paper describes a variable output voltage, multi-phase switched capacitor step-up DC-DC converter with a digital voltage regulation scheme, implemented in CMOS VLSI technology. The number of conversion ratios generated using n flying capacitors is of the order of 2n. A scheme for selection of switch is presented. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency are obtained and compared with the cadence spectre simulation results. The step-up open loop converter circuit for one of the gain is described and analysed by varying the switching frequency. An open loop converter efficiency of about 78% is achieved with 4% bottom plate parasitic capacitance for a load current of 1 mA and input voltage of 0.6 V at 4 MHz of switching frequency for a gain of 4/3. The voltage regulation scheme for a desired output voltage is designed with a digital control circuit using inherent capacitive DAC which can interpolate through various gain configuration for n = 2 flying capacitor and is simulated in Cadence Analog-Mixed Signal Flow using 180nm CMOS technology. The layout design using MIM cap has been done and back annotation results are presented.

Design of CMOS programmable output binary and fibonacci switched capacitor step-down DC-DC converter

This paper describes the CMOS implementation of an open-loop variable output voltage switched capacitor step-down DC-DC converter with a large number of target voltages. The number of target voltages generated using n-flying capacitors are of the order of 2n. A switch selection scheme is presented that optimizes silicon area. Expressions for equivalent series resistance Req, conduction, switching power loss and efficiency are obtained and compared with the spice simulation results. The Digital Switch Controller is designed to switch between various target voltages and simulated in Cadence Analog-Mixed Signal flow. The 3/4 step-down converter circuit is described and analysed by varying switching frequency and load for different values of bottom plate parasitic capacitance. The optimum value of switching frequency and switch sizes is obtained for a switched capacitor converter. An efficiency of about 78.4% is achieved with 5% bottom plate parasitic capacitance for a load current of 1.35 mA and input voltage of 1.8 V at 20 MHz of switching frequency.

Analysis of Tracking Distortion in Bootstrapped Gate MOSFET Sample-hold Circuits and a Method for its Minimization

Abstract A theory for the analysis of tracking distortion using the Volterra series is developed for bootstrapped gate sample-hold circuits with arbitrary signal AC gain applied at the gate. It is shown that second (HD2) and third (HD3) harmonic distortion show zeroes (minima) with respect to bootstrap gain whose location depends upon gate and substrate bias. Furthermore, the HD2 minimum occurs when the body-effect is compensated by applying a gain equal to the subthreshold slope factor of the MOSFET. These results are verified by using simple physics-based strong-inversion and surface-potential models as well as the PSP compact model. The cases of distortion and phase-lag in the bootstrap gate path are also considered. Measured second harmonic distortion on a discrete prototype shows reasonable agreement against simulation results using extracted MOSFET model parameters.

Programmable Output Multi-phase Switched Capacitor Step-Up DC-DC Converter with SAR-based Regulation

This paper describes the CMOS implementation of the variable output voltage, multi-phase switched capacitor step-up DC-DC converter with SAR-based regulation scheme. The number of target voltages generated using n-flying capacitors is of the order of 2n. A scheme for selection of switch is presented. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency are obtained and compared with the spice simulation results. The converter has an inherent capacitive DAC that can be used for digital gain control along with a comparator to get the desired output voltage. The step-up open loop converter circuit for the gain of 4/3 is described and analysed by varying the switching frequency. An open loop converter efficiency of about 78% is achieved with 4% bottom plate parasitic capacitance for a load current of 1 mA and input voltage of 0.6 V at 4 MHz of switching frequency. The digital control circuit using inherent capacitive DAC is designed and simulated in Cadence Analog-Mixed signal flow. The layout design using MIM cap has been done and back annotation results are presented.

Programmable output switched capacitor step-down DC-DC converter with high accuracy using Sigma-Delta Feedback Control Loop

This paper describes the CMOS implementation of variable output voltage, multiphase switched capacitor step-down DC-DC converter with a large number of target voltages using Sigma-Delta Feedback Control Loop. The number of target voltages generated using n-flying capacitors are of the order of 2n. Expressions for equivalent series resistance Req, conduction, switching power loss and efficiency are obtained and compared with the spice simulation results. The Sigma-Delta Feedback Control Loop is designed which automatically switch between various target voltages and simulated in Cadence Analog-Mixed Signal flow. The Sigma-Delta feedback controller has a very high gain at DC and hence gives higher accuracy as compared to alternative methods. The 3/4 step-down converter circuit is described and analyzed by varying switching frequency and load for different values of bottom plate parasitic capacitance. An efficiency of about 77.3% is achieved with 10% bottom plate parasitic capacitance for a load current of 135 uA and input voltage of 1.8 V at 2 MHz of switching frequency. The load regulation of 7.33 mV/mA and line regulation of 6.5 mV/V is achieved.

Switch selection & sizing in CMOS implementation of variable output switched capacitor step-down DC-DC converter

This paper describes the CMOS implementation of an open-loop variable output voltage switched capacitor step-down DC-DC converter with large number of target voltages. The number of target voltages generated using n-flying capacitors are of the order of 2n. A scheme for selection of transistor type and size is given that optimizes silicon area and efficiency of a given design. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency are derived in terms of switching frequency (Fsw), flying capacitor value and compared with the simulated results. The effect of flying capacitor on efficiency is shown with the plots of efficiency vs. output voltages and bottom plate capacitance. The 3/4 step-down converter circuit is described and analysed by varying switching frequency and load for different values of bottom plate capacitance. An efficiency of about 87% is achieved with 15% bottom plate capacitance for load current of 10mA and input voltage of 1.8V at 4MHz of switching frequency.

A low voltage cascode biasing circuit with gain-boosting

This paper proposes a new cascode current source circuit that provides high-gain with improved headroom and is suitable for low-voltage amplifiers. The circuit achieves this by modifying a low-voltage cascode gate biasing circuit (“trickle-bias”) such that it amplifies the voltage of the cascode node using a PMOS input folded gain-boost amplifier. The low-voltage current source operates down to 260 mV while providing an improvement of output impedance by a factor of 2.5 as compared to a conventional current source. The proposed cascode current source has been applied to an NMOS input folded-cascode amplifier that gives a gain of 63 dB with a unity-gain frequency of 22.1 MHz at a phase-margin of 64.8° with a total bias current of 30μA operating at a supply voltage of 1.8V.

Development of 3D shadow mask using 3D printer

Recent emergence of 3D printing technology has made the fabrication of unconventional micron scale structures possible. The shadow mask is a typical high aspect ratio 3D structure used to deposit metal patterns. Shadow masks are generally laser drilled on metallic substrate or hard baked patterned resist. A novel method of shadow mask preparation using an educational Makerbot 3D printer is discussed and experimental results are analyzed in this paper. The shadow mask was effectively used in a high vacuum deposition unit to transfer copper patterns on glass substrate. The accuracy and deviations in the printed aperture size of shadow mask and copper patterns transferred on the glass substrate are demonstrated via experimental results. Three sets of aperture widths: 300, 350 and 400 μm were designed and printed into two plastic masks of 400 and 700 μm thickness. 350 μm aperture width in the mask demonstrated less variation and copper line width obtained from pattern transfer process was measured close to the designed width. High aspect ratio structures were difficult to print due to the additive nature of 3D printing process. Shadow deposition effect was reduced for deeper sidewalls based slots in the mask. The inter-slot study indicated that 3D printed effective mask spacing on either side of apertures increases for thicker mask. The yield of the ABS deposited mask is observed to be poorer for the thicker (700 um) mask as compared to thinner mask. In general it can be concluded that 350 μm width resolution masks can be reliably fabricated at 400 μm thickness using this method. The 3D printing method explained in this paper is a feasible and economically viable approach to develop shadow mask for organic and plastic electronics applications.

A distortion reduction technique for bootstrapped-gate MOS Sample-and-Hold circuits using body-effect compensation

A distortion improvement technique for bootstrapped-gate Sample-and-Hold (S/H) circuits, is proposed. The gate overdrive voltage and conductance of the MOS sampling switch are made constant by cancelling the body-effect induced variations in the threshold-voltage. An amplifier is used to provide appropriate gain in the bootstrapped-gate path. The technique allows the minimized second-harmonic distortion (HD2) by adjusting the gain to Ag =1+kγ1, where kγ1 is the sensitivity of threshold voltage to the source voltage. Furthermore, the S/H distortion remains insensitive to the amplifier op-amp characteristics. Chip prototype measurement results of a single-ended S/H amplifier using 0.18 μm CMOS technology show HD2 improvement of 11 dB over conventional bootstrapped-gate S/H.