Bouraoui Ouni

An efficient list scheduling algorithm for time placement problem

The partially reconfigurable FPGAs allows an overlap between the execution and the reconfiguration of tasks. The partial approach can be used to fit a large application into the FPGA device by partitioning the application over time. The executions being partitioned over time and the configurations of tasks are done so that the imposed constraints are satisfied. The main aim of this work consists in answering the question when will a task be mapped in the FPGA? A time placement algorithm based on the list scheduling technique is developed to solve efficiently the above question. We have just used the list scheduling algorithm because of its fast run time. Compared to the run time of other algorithms used in this filed like the spectral and ILP algorithms, the list scheduling algorithm remains a good temporal placement candidate, especially, for a several nodes graph. Also, a part of this paper is devoted for the study and the implementation of DCT task graph. This graph is the most computationally intensive part of the Color Layout Descriptor algorithm of a low-level visual descriptor of MPEG 7. The studied case shows that the use of the partial approach is very efficient in terms of latency of the whole application than the full one.

Synthesis and Time Partitioning for Reconfigurable Systems

This paper aims to introduce a time partitioning algorithm which is an important step during the design process for fully reconfigurable systems. This algorithm is used to solve the time partitioning problem. It divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal. Also a part of this paper is consecrated for implementation of some examples on a fully reconfigurable architecture following our approach.

Temporal partitioning of data flow graph for dynamically reconfigurable architecture

Abstract In this paper, we present a novel temporal partitioning algorithm that temporally partitions a data flow graph on reconfigurable system. Our algorithm can be used to resolve the temporal partitioning problem at the behaviour level. Our algorithm optimizes the whole latency of the design; this aim can be reached by minimizing the latency of the graph and the number of partitions at the same time. Consequently, our algorithm starts by the lowest possible number of partitions; and next it uses the eigenvectors of the graph to find the best schedule of nodes that minimizes the latency of the graph. The proposed methodology was tested on several examples on reconfigurable architecture based on Xilinx Vertex-II XC2V1000 FPGA device. The results show significant reduction in the design latency compared to famous related algorithms used in this field.

Partitioning and scheduling technique for run time reconfigured systems

With tremendous improvement in FPGA technologies over the last decade, various high performances, low cost FPGAs are now available. This has enabled the development of cost effective, high speed reconfigurable boards called run time reconfigured (RTR) system. These boards, due to the abundant hardware resource available, enhance the amount of design parallelism by several magnitudes in comparison to ASIC designs of comparable cost. The advent of such high performance FPGA boards has brought a new research problem: the temporal partitioning problem. In the literature, the main objective of related algorithms in this field is to find the minimal execution time of the input graph on a fixed-size of area. However, this paper focuses on introducing a new temporal partitioning algorithm. It divides the input task graph into an optimal number of partitions and puts each task in the appropriate partition in order to decrease the transfer of data required between partitions of the design.

Combining temporal partitioning and temporal placement techniques for communication cost improvement

In this paper, we present a typical temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable system. Our approach optimizes the communication cost of the design. This aim can be reached by minimizing the transfer of data required between design partitions and the routing cost between FPGA modules. Consequently, our algorithm is composed by two main steps. The first step aims to find a temporal partitioning of the graph. This step gives the optimal solution in term of communication cost. Next, our approach builds the best architecture, on a partially reconfigurable FPGA, that gives the lowest routing cost between modules. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field.

MEMS SPDT microswitch with low actuation voltage for RF applications

Purpose – This paper aims to propose a novel design of an ohmic contact single-pole double-throw (SPDT) microelectromechanical system (MEMS) microswitch for radio frequency applications. Design/methodology/approach – The proposed microswitch (SPDT design) shares antenna between transmitter and receiver in a wireless sensor. An electrical voltage is used to create an electrostatic force that controls the ON/OFF states of the microswitch. First, the authors develop a mathematical model of the proposed microswitch and propose a reduced-order model of the design, based on the differential quadrature method, which fully incorporates the electrostatic force nonlinearities. The authors solve the static, transient and dynamic behavior and compare the results with finite element solutions. Then, the authors examine the dynamic solution of the switch under different actuation waveforms. Findings – The obtained results showed a significant reduction in actuation voltage, pull-in bandwidth and switching time. Origina...

Exploring the temporal placement for partially reconfigurable device

In this paper, we examine the temporal placement, showing how it can be decomposed into a number of distinct but not independent subtasks. Then, we detail the early algorithms that have been developed for solving the temporal placement problem. Next we introduced a new temporal placement algorithm that aims to reduce the routing cast between modules. And finally, experiments are conducted in order to evaluate the complexity and design performances of the proposed algorithm versus others temporal placement algorithms.

Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Shortening the marketing cycle of the product and accelerating its development efficiency have become a vital concern in the field of embedded system design. Therefore, hardware/software partitioning has become one of the mainstream technologies of embedded system development since it affects the overall system performance. Given today’s largest requirement for great efficiency necessarily accompanied by high speed, our new algorithm presents the best version that can meet such unpreceded levels. In fact, we describe in this paper an algorithm that is based on HW/SW partitioning which aims to find the best tradeoff between power and latency of a system taking into consideration the dark silicon problem. Moreover, it has been tested and has shown its efficiency compared to other existing heuristic well-known algorithms which are Simulated Annealing, Tabu search, and Genetic algorithms.

Fatal anaphylactic reaction to intravenous infusion of Ondansetron: a report of two cases

Ondansetron is a selective 5 hydroxy-tryptamine 3 (5-HT3) receptor antagonist widely used as an effective antiemetic drug especially for the prevention of chemotherapy-induced nausea and vomiting [1]. The efficacy of ondansetron has been reported in several studies and it is reported to be a well-tolerated drug [2]. The most common side effects reported to ondansetron are headaches, diarrhea, constipation, fever and dizziness [3-5]. Anaphylactic reaction to ondansetron is rarely reported [6,7]. Abstract

Online Adaptive Filters to Classify Left and Right Hand Motor Imagery

Sensorimotor rhythms (SMRs) caused by motor imagery are key issues for subject with severe disabilities when controlling home devices. However, the development of such EEG-based control system requires a great effort to reach a high accuracy in real-time. Furthermore, BCIs have to confront with inter-individual variability, imposing to the parameters of the methods to be adapted to each subjects. In this paper, we propose a novel EEG-based solution to classify right and left hands(RH and LH) thoughts. Our approach integrates adaptive filtering techniques customized for each subject during the training phase to increase the accuracy of the proposed system. The validation of the proposed architecture is conducted using existing data sets provided by BCI-competition and then using our own on-line validation platform experienced with four subjects. Common Spatial Pattern (CSP) is used for feature extraction to extract features vector from µ and I² bands. These features are classified by the Linear Discriminant Analysis (LDA) algorithm. Our prototype integrates the Open-BCI acquisition system with 8 channels connected to Matlab environment in which we integrated all EEG signal processing including the adaptive filtering. The proposed system achieves 80.5% of classification accuracy, which makes approach a promising method to control an external devices based on the thought of LH and RH movement.