Mehdi Jemai

Hardware software partitioning of control data flow graph on system on programmable chip

A System On Programmable Chip (SOPC) is a circuit that integrates all components of an electronic system into a single chip. It may consist of memories, one or more microprocessors, interface devices, configurable logic blocks and other necessary components to achieve an intended function. In this paper, we propose a new hardware-software partitioning algorithm of control data flow graph for SOPC. The main aim of our algorithm is to find a best compromise between hardware and software implementation of operations in order to satisfy design constraints in terms of latency and hardware resources of the target application. Our algorithm has been evaluated on real hardware device. In fact, experimentations have been done using a real FPGA Virtex-5. Results have shown that our algorithm provides a better performing system with the lowest possible cost compared to existing approaches.

Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Shortening the marketing cycle of the product and accelerating its development efficiency have become a vital concern in the field of embedded system design. Therefore, hardware/software partitioning has become one of the mainstream technologies of embedded system development since it affects the overall system performance. Given today’s largest requirement for great efficiency necessarily accompanied by high speed, our new algorithm presents the best version that can meet such unpreceded levels. In fact, we describe in this paper an algorithm that is based on HW/SW partitioning which aims to find the best tradeoff between power and latency of a system taking into consideration the dark silicon problem. Moreover, it has been tested and has shown its efficiency compared to other existing heuristic well-known algorithms which are Simulated Annealing, Tabu search, and Genetic algorithms.

Meta-heuristics: For the problem of partitioning hardware/software

In recent years, several meta-heuristics have proved their effectiveness in solving combinatorial problems such as hardware / software partitioning. In this paper, we present a synthesis of main meta-heuristics: local search methods and evolutionary algorithms. We offer an analysis of these meta-heuristics by identifying the fundamental ideas guiding the choice of a meta-heuristic in practice.

Scheduling algorithm for digital systems to optimize dynamic power

In this paper we have developed a new scheduling algorithm that provides a decrease in dynamic power consumption through achieving components scheduling. The major idea of that algorithm is to amplify the latency of some components whenever it is feasible without negatively influencing the dependency constraints. For that purpose, we have decreased the frequency of the components clocks. Since frequency and power are inter-related, a decrease in frequency value will be followed by a decrease in power consumption. Our algorithm has been tested and has given an interesting gain in dynamic power.