Bradley S. Carlson

Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs

An algorithm is presented to determine two lower bounds in functional pipelined data path synthesis. Given an iteration time constraint and a task initiation latency, the algorithm computes a lower bound on the number of functional units required to execute the data flow graph (DFG) of a loop body, and given a resource constraint and a task initiation latency the algorithm computes a lower bound on the number of time steps required to execute the DFG. The lower bounds not only greatly reduce the size of the solution space, but also provide a means to measure the proximity of the final solution to an optimal one. The bounds are computed in polynomial time; therefore the algorithm is very effective, especially for large DFGs. Experiments indicate that the lower bound is very tight. For all of the test cases the difference between our solution and the optimal solution is not greater than one.<<ETX>>

Delay optimization of digital CMOS VLSI circuits by transistor reordering

In this paper the effects of transistor reordering on the delay of CMOS digital circuits are investigated, and an efficient method which uses transistor reordering for the delay optimization of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area and power dissipation. The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay. Experimental results for benchmark circuits are given in 2.0, 1.2, and 0.8 /spl mu/m CMOS technologies. The average improvement in delay for the 20 benchmarks used in this paper is 9.1%. >

Improved lower bounds for the scheduling optimization problem

In this paper lower bounds for the performance constrained and resource constrained scheduling of tasks on multiprocessors are presented. The lower bounds derived here are sharper than previously known results and the time complexity of their computation is only slightly greater.<<ETX>>

Critical voltage transition logic: an ultrafast CMOS logic family

The authors present a new kind of CMOS logic circuit that has a different structure and different operation mechanism compared to the existing logic circuits. Its unique delay propagation characteristic makes it much faster than the conventional CMOS logic gate. Gate outputs are preconditioned to a voltage level between V/sub dd/ and V/sub ss/ using a new clocking scheme and circuit design. They give a buffer design example which is about 6.5 times faster than the conventional buffer. The total energy consumed by the new circuit structure is slightly more than conventional CMOS domino logic; however the energy-delay product is smaller.

Synthesis of SEU-tolerant ASICs using concurrent error correction

We present a new design technique for the concurrent error correction of single event upsets in the memory elements of ASICs. The technique uses a single error correction/double error detection (SEC/DED) Hamming code to encode the content of the memory elements. The area and delay overhead and error-correction capability are optimized by partitioning the set of memory elements. Design experiments show our technique is feasible, and it can be applied to any ASIC technology.

CMOS read-out IC with op-amp pixel amplifier for infrared focal plane arrays

The design and prototype of a read-out integrated circuit for an uncooled infrared focal plane array are described in this paper. The device is designed to interface to a pyroelectric infrared detector array of size 320/spl times/240. The read-out IC presented here achieves better performance and uniformity compared to existing approaches by implementing a single stage CMOS op-amp within each pixel of the detector array. The prototype devices exhibit fixed pattern noise less than 5 mv (0.5% of full scale) without correction. The pixel amplifier exhibits less than 0.6% maximum (0.5% average) relative gain error with less than 0.2% gain variation over the 1 V input range.

Analysis and experimental results of a CVTL buffer design

We present experimental results for a new CMOS logic family: Critical Voltage Transition Logic (CVTL). It has a different structure and different operating characteristic compared to existing CMOS logic circuit families. Its novel delay propagation characteristic makes it much faster than the conventional CMOS logic gate. Measurements show that the CVTL buffer is four to eight times faster than the static counterpart. Although it consumes more energy, the energy-delay product is significantly smaller compared with a static CMOS buffer.

A VLSI circuit design course for practitioners and researchers

Graduate students can usually be classified in two categories: research engineers and practicing engineers. The microelectronic systems education of these two groups of students have different objectives. This paper describes a one semester course developed to meet the objectives for both groups of students. The course lectures cover custom and semicustom CMOS VLSI circuit design, and the laboratory utilizes a mixture of public domain and commercial CAD tools.

Transistor chaining in CMOS leaf cells of planar topology

A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of non-series/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82% of the circuits tested, and has linear time complexity.

An efficient algorithm for the identification of dual Eulerian graphs and its application to cell layout

A linear time algorithm which identifies the dual Eulerian property in a plane undirected multigraph is presented. This graph property is important in the generation of layouts of CMOS circuits for VLSI design. A linear time heuristic algorithm is presented for the more general dual path cover problem which is known to be NP-hard. The algorithm operates on non-series/parallel graphs in addition to series/parallel graphs, determines very good solutions and its time complexity is linear with respect to the number of edges in the graph. The algorithm has produced optimal results for more than 80% of over 300 test cases.<<ETX>>