C.Y.R. Chen

Optimal algorithms for bubble sort based non-Manhattan channel routing

It has been pointed out that, in many cases, results generated by non-Manhattan channel routers will be better than those generated by Manhattan routers. Non-optimal bubble sort based algorithms for non-Manhattan channel routing have been proposed in the literature by also allowing connections in the +45/spl deg/ and /spl minus/45/spl deg/ directions. In this paper, optimal algorithms are proposed for the two-layer and three-layer non-Manhattan channel routing problems based on an identical problem formulation. The time complexities of our algorithms and the existing algorithm (which produces the best results so far) are O(K/sup 2/ * N) and O(K * N/sup 2/), respectively, where N is the number of terminals (i.e., the length) of the channel and N is the number of routing tracks (i.e., the height) in the channel. K is always less than N, and in most cases is much smaller than N. Clearly, a significant improvement in time complexity over the existing algorithm (which produces the best results so far) is achieved, while ensuring optimality. >

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering

A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic power dissipation. In particular, excellent results have been achieved when the method is applied to data path circuits.

Efficient Boolean matching algorithm for cell libraries

An efficient algorithm for searching for functional cells based on Boolean matching in a large library is presented. Redundant variables and permutation of inputs are considered in this algorithm. The algorithm does a search in constant time, independent of the size of the library.<<ETX>>

A pin permutation algorithm for improving over-the-cell channel routing

A dynamic-programming-based algorithm is presented to determine proper gate and terminal positions such that, when over-the-cell routers are used, the area above and below the channel can be utilized more effectively and the channel density can be greatly reduced. The problem formulation and previous work are discussed. The terminology and notation are introduced. A polynomial-time algorithm is presented. Experimental results showed that the proposed algorithm considerably reduces the channel density.<<ETX>>

Diffusion sharing across cell boundaries in cell based design

A layout design often contains regular, repeatable or iterative structures, and datapath is an example of such a design-style. Designers take advantage of regularity by using library cells for density and productivity improvements, This study is aimed at studying the impact on overall density due to diffusion sharing across cell boundaries. Often the library cell area is optimized without comparing the global impact on the assembled design. We compare two methods of designing cells, a practically used one and an intuitively desired one. We show that the intuitive method is not always feasible and that a hybrid method of designing a cell is optimal. Studies on real examples have shown the gains to be made in density by diffusion sharing across cell boundaries. We also present situations in which the diffusion sharing causes a loss of overall density. The conclusion is a set of guidelines on when to use diffusion sharing among the library cells.

Effects of transistor reordering on the performance of MOS digital circuits

The effect of transistor reordering on the tuning behavior of MOS circuits is investigated. The investigation is performed by analyzing the transient response of series connected MOS structures (SCMSs) using SPICE. The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time. Circuits for which the effect of transistor reordering on timing is insignificant are clearly identified.<<ETX>>

Optimal cell generation for dual independent layout styles

Many optimization algorithms have been proposed for layout styles which are dual dependent: that is, the optimization for the layout of the n-transistor network of a CMOS complex gate is dependent on, the p-transistor network and vice versa. A two-stage linear-time optimization algorithm for dual independent layout styles is presented. The first stage is based on a tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization goal is identical to the Euler pathed optimization algorithms metal-metal matrix (M/sup 3/) layout style, and examples of generated layouts are shown. Starting from a switching expression, the proposed algorithm always produces an optimal solution in terms of the number of diffusion breaks, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence to traverse this transistor circuit (second stage). >

Detailed placement with net length constraints

Increasing demands created by Systems-On-Chip (SOC) and process advances have increased the difficulty of timing driven placement. The primary issue in SOC is timing closure. This requires us to look at timing at all design levels, especially placement. Recently, several promising approaches for timing-driven placement have been presented using net length constraints for timing optimization (Alpert et al., 2001). A Net Length Constraint (NLC) is an upper limit on a nets length. These net-constrained global placement techniques give excellent timing results by meeting NLCs on timing-critical nets. These works focused only on global NLC placement. Detailed placement and legalization are important steps in the placement flow. Current algorithms, which are not NLC aware, give back the gains from global NLC placement. The contributions of this paper are a new NLC global placement rebalancing method and two detailed placement algorithms that work in conjunction with the recursive bisection net-constrained global placer (Alpert et al., 2001). The first detailed placer uses grid-based placement and transportation solving to assign instances to the grid. The second detailed placer uses simulated annealing to optimize placement for NLC. On benchmark circuits from MCNC and Intel Corporation, the grid and simulated annealing placers are able to achieve placements which exceed constraints by, on average only, 2.7% and 1.9%, respectively.

From logic to symbolic layout for gate matrix

Gate matrix is a style which allows random logic layout to be performed in a regular manner. An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous work which uses dynamic net list and the concept of delayed binding performs only a small subset of the reordering possible with the proposed algorithm. The proposed algorithm uses a net-list-independent technique to determine the gate sequence. An optimized net list is created after the gate sequence is known. The algorithm has a time complexity of O(E log E) for a design with E logic equations. The experimental results show a considerable reduction in layout area. >

Methodologies for designing video servers

This paper proposes an approach for integrating CPU/disk/network scheduling and memory management for supporting a variety of VCR operations and dynamic service changes efficiently. Under this approach we can optimize individual resources, and support a maximal number of clients on a given system. We present a framework of service modeling to characterize the requested video services and identify the scheduling parameters for supporting these services. A number of techniques and methodologies are developed for analyzing the behaviors of disk accesses, network operations, and CPU activities under the loads of both single and multiple clients. We also describe an admission control strategy that utilizes information about all the system resources to determine if a set of video services is acceptable.