Brady Benware

Impact of multiple-detect test patterns on product quality

Abstract This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects. Volumedata obtained by testing a production ASIC with these new multiple-detect patterns shows increased defect screening capability and very good agreement with the bridging coverage estimated by the ATPG tool. 1. Introduction One of the key objectives of manufacturing test is to ensure high quality of shipped parts while managing the cost of test. Scan–based DFT methodology, combined with ATPG tools, automate the generation of test patterns with very high fault coverage. The advantage ofa structure-based ATPG tool is its high efficiency and effectiveness in generating a test set by targeting different fault models, such as stuck-at, transition, path delay, and DDQ . DFT tooI ls assess the quality of test patterns by reporting the fault coverage of the target fault models. However, real defects may not always be detected by test patterns generated for the targeted fault model. The stuck-at fault model has been used in DFT ince sthe very beginning and, while showing some limitations and imperfections, it has demonstrated its robustness and adaptability. Even though the stuck-at fault model may not always model behavior of a faulty circuit it serves very well as a target, i.e. a test set developed to test stuck-at faults will also cover many other defects that do not behave as stuck-at faults. Good understanding of bridging defects is at the center of explanation of the effectiveness of the stuck-at fault model. It also provides the key clues to its enhancements. In an experimental study of bridging faults in a state of the art microprocessor design [1] it has been observed that approximately 80% of all bridges occur between a node and Vcc or Vss, and 20% involve nonsupply nod- es. Global signals were involved in 70% of these defects and leaf-level signals contributed only 30%. In another experimental evaluation of scan tests for bridging defects [2] it was concluded that bridges with power rails contributed between 60% to 90% of all bridging defects. It is clear that a test that detect a stuck-at fault on a node willdetect a low resistive bridging defect with the supply lines. This is exactly the behavior of a node stuckat- -0 or stuckat- -1. However, the detection of node-to-node bridging defects is not guaranteed. If a stuckat fault on a node is detected once, the- probability f detecting a static bridging fault witho another un-correlated node that has signal probability 50% is also 50% [3].If the stuck at fault is detected- twice, the estimated probability of detecting the bridging fault with another node acting as an aggressor is 75%. Signal correlation may reduce the coverage of nodeto-node bridging faults. It was- observed [1] that a test set with greater than 95% stuck-at fault coverage produced only 33% coverage of nodeto-node bridging faults. Most likely the- disappointing coverage was an artifact of signal correlation. Typically a test set created by conventional ATPG aiming at single detection may have up to 6% of faults detected only once and up to 10% of faults detected only once or twice. This may result in inadequate coverage of nodeto-node -bridging defects. In general, there are two directions to overcome the limitation and improve the test quality. One direction is to enhance the fault model by describing the defect behavior and presenting it in a suitable form to the ATPG tool. In this case the fault model is more precise and complex and the fault list s longer. Thei advanced fault models, like bridging faults and cross-talk effects, use physical layout information to compile the fault lists. A complete example of this approach is demonstrated in [2]. Here the possible bridges are identified by analysis of layout using weighted critical area and their behavior is modeled by different types of faults and a special netlist. The experimental results from the project show that

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis

This paper presents a flow for using logic diagnosis to turn production material into vehicles for yield learning. High throughput logic diagnosis is combined with the newly emerging field of design for manufacturing to enable layout aware diagnosis. The ability of the flow to calculate feature failure rates and the application of the failure rates for yield learning is demonstrated through volume data analysis on a production ASIC

In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test cost

Maintaining product quality at reasonable test cost in very deep sub-micron process has become a major challenge especially due to multiple manufacturing locations with varying defect and parametric distributions. Increasing vector counts and binary search routines are now necessary for subtle defect screening. In addition, parametric tests and at-spec testing is still often necessary to ensure customer quality. Systematic defects are becoming more common and threaten to dominate the yield Pareto. Adaptive test methods are introduced in This work that demonstrate the capability of increasing or decreasing the test coverage based on the predicted or measured defect and parametric behavior of the silicon being tested. Results promise an increase in product quality at the same time a reduction in test costs.

Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs

In sub-micron processes, resistive path defects are increasingly contributing to the yield loss and the customer fail pareto. Data has been collected on a series of ASIC products and it has been used to compare the effectiveness of full vector set transition delay fault tests with reduced vector sets, minVDD, customer functional tests and customers system fails. Results show that fault models do not predict the defect coverage well and cost effective screening of frequency outliers and minVDD outliers is possible and is critical in improving customer quality.

Obtaining high defect coverage for frequency-dependent defects in complex ASICs

Structured delay tests have been around for years, but how effectively do they identify defective silicon, even at reduced frequency? How much overkill is associated with their use? The authors present data from industrial circuits aimed at these and other aspects of speed testing.

Affordable and effective screening of delay defects in ASICs using the inline resistance fault model

Transition delay fault (TDF) testing has become a necessary test method in very deep sub micron (VDSM) technologies due to the presence of resistive defects that cause subtle timing failures. The transition delay fault model is based on a slow-to-rise and slow-to-fall fault at each node in the circuit. Some resistive defects such as resistive vias actually induce both faults and the TDF test set can contain unnecessary test patterns for proper screening of this type of defect. The inline resistance fault (IRF) model more accurately represents this defect type and is studied in depth in This work. ATPG experimental results show that IRF patterns can be generated 1.4 to 1.8 times faster with 45% to 58% fewer patterns than traditional TDF patterns. IRF and TDF pattern test results are presented and show that the more expensive TDF remains a more comprehensive test than IRF as expected, but that the quality impact of using only the IRF test set is minimal, especially when combined with effective IDDQ outlier screening such as statistical post processing. Additionally, a methodology is presented for the determination of the number of delay defects that behave according to each model from the test data alone, which is necessary to accurately determine delay defect coverage from multiple test coverage metrics.

Defect screening using independent component analysis on I/sub DDQ/

An I/sub DDQ/ Statistical Post-Processing/spl trade/ (SPP) outlier screen is presented based on the computation of statistically independent sources of variation in the I/sub DDQ/ measurements. I/sub DDQ/ measurements from die passing all other tests are modeled using sources of variation extracted by independent component analysis (ICA). Outliers are separated from the sample population based on residuals computed using these sources and a nearest neighbor spatial signature. An algorithm is presented for applying the proposed technique in production. The screen is demonstrated with 0.18/spl mu/m and 0.11/spl mu/m volume data and shown to effectively identify the outliers at the 0.1 /spl mu/m technology node.

Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis

Traditional yield analysis has been focused on wafer fabrication and process improvement and is generally limited to wafer level visualization. As products get more complex and design practices have more impact on yield, visualization of yield issues inside the chip becomes increasingly critical. This paper presents novel visualization and analysis of volume structural test fail data to aid in the identification of yield weaknesses through relative analysis of fail signatures. The results show that these methodologies can identify subtle process/design yield limiters which cannot be identified using traditional yield analysis methodologies

The value of statistical testing for quality, yield and test cost improvement

This paper is the third in a lecture series on statistical analysis of semiconductor test data. Statistical test methods offer increased value in IC manufacturing and test over traditional maverick silicon screening methods by optimizing the trade-off between yield and reliability in deep sub-micron CMOS technologies. Effective use of the vast volume of data generated by test can lead to cost-effective screening of subtle defects, burn-in reduction or elimination and test cost reduction through adaptive test

Screening vdsm outliers using nominal and subthreshold supply voltage I/sub DDQ/

Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-Processing™ (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under Test (DUT) and takes two quiescent current measurements. The quiescent current measurements are taken at nominal and at subthreshold supply voltages. The scr een is demonstrated with 0.18µm and 0.13µm volume data. The screens effectiveness is compared to stuck -at and other IDDQ screens.