Robert Madge

Neighbor selection for variance reduction in I/sub DDQ/ and other parametric data

The subject of this paper is variance reduction and nearest neighbor residual estimates for I/sub DDQ/ and other continuous-valued test measurements. The key, new concept introduced is data-driven neighborhood identification about a die to reduce the variance of good and faulty I/sub DDQ/ distributions. Using LSI Logic production data, neighborhood selection techniques are demonstrated. The main contribution of the paper is variance reduction by the systematic use of the die location and wafer- or lot-level patterns and improved identification of die outliers of continuous-valued test data such as I/sub DDQ/.

Screening minVDD outliers using feed-forward voltage testing

MinVDD testing using full vector set search routines consumes too much test time. A 3-step process is proposed using: (1) a reduced vector set (RVS) binary search to measure the intrinsic (defect free) minVDD for a die; (2) a feed-forward to the full vector set (FVS) for low voltage testing; and (3) delta VDD and nearest neighbor residual statistical post-processing (SPP) are applied to the data to screen the minVDD outliers that are identified using the RVS binary search. RVS vs. FVS correlation data is shown on 3 products. Data shows minVDD yield fallout of 0.2-0.8% and 20% of the minVDD outliers shows significant VDD shifts in burn-in.

In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test cost

Maintaining product quality at reasonable test cost in very deep sub-micron process has become a major challenge especially due to multiple manufacturing locations with varying defect and parametric distributions. Increasing vector counts and binary search routines are now necessary for subtle defect screening. In addition, parametric tests and at-spec testing is still often necessary to ensure customer quality. Systematic defects are becoming more common and threaten to dominate the yield Pareto. Adaptive test methods are introduced in This work that demonstrate the capability of increasing or decreasing the test coverage based on the predicted or measured defect and parametric behavior of the silicon being tested. Results promise an increase in product quality at the same time a reduction in test costs.

Obtaining high defect coverage for frequency-dependent defects in complex ASICs

Structured delay tests have been around for years, but how effectively do they identify defective silicon, even at reduced frequency? How much overkill is associated with their use? The authors present data from industrial circuits aimed at these and other aspects of speed testing.

Affordable and effective screening of delay defects in ASICs using the inline resistance fault model

Transition delay fault (TDF) testing has become a necessary test method in very deep sub micron (VDSM) technologies due to the presence of resistive defects that cause subtle timing failures. The transition delay fault model is based on a slow-to-rise and slow-to-fall fault at each node in the circuit. Some resistive defects such as resistive vias actually induce both faults and the TDF test set can contain unnecessary test patterns for proper screening of this type of defect. The inline resistance fault (IRF) model more accurately represents this defect type and is studied in depth in This work. ATPG experimental results show that IRF patterns can be generated 1.4 to 1.8 times faster with 45% to 58% fewer patterns than traditional TDF patterns. IRF and TDF pattern test results are presented and show that the more expensive TDF remains a more comprehensive test than IRF as expected, but that the quality impact of using only the IRF test set is minimal, especially when combined with effective IDDQ outlier screening such as statistical post processing. Additionally, a methodology is presented for the determination of the number of delay defects that behave according to each model from the test data alone, which is necessary to accurately determine delay defect coverage from multiple test coverage metrics.

Defect screening using independent component analysis on I/sub DDQ/

An I/sub DDQ/ Statistical Post-Processing/spl trade/ (SPP) outlier screen is presented based on the computation of statistically independent sources of variation in the I/sub DDQ/ measurements. I/sub DDQ/ measurements from die passing all other tests are modeled using sources of variation extracted by independent component analysis (ICA). Outliers are separated from the sample population based on residuals computed using these sources and a nearest neighbor spatial signature. An algorithm is presented for applying the proposed technique in production. The screen is demonstrated with 0.18/spl mu/m and 0.11/spl mu/m volume data and shown to effectively identify the outliers at the 0.1 /spl mu/m technology node.

Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis

Traditional yield analysis has been focused on wafer fabrication and process improvement and is generally limited to wafer level visualization. As products get more complex and design practices have more impact on yield, visualization of yield issues inside the chip becomes increasingly critical. This paper presents novel visualization and analysis of volume structural test fail data to aid in the identification of yield weaknesses through relative analysis of fail signatures. The results show that these methodologies can identify subtle process/design yield limiters which cannot be identified using traditional yield analysis methodologies

Neighborhood selection for I/sub DDQ/ outlier screening at wafer sort

To screen defective dies, I/sub DDQ/ tests require a reliable estimate of each dies defect-free measurement. The nearest-neighbor residual (NNR) method provides a straightforward, data-driven estimate of test measurements for improved identification of die outliers.

The value of statistical testing for quality, yield and test cost improvement

This paper is the third in a lecture series on statistical analysis of semiconductor test data. Statistical test methods offer increased value in IC manufacturing and test over traditional maverick silicon screening methods by optimizing the trade-off between yield and reliability in deep sub-micron CMOS technologies. Effective use of the vast volume of data generated by test can lead to cost-effective screening of subtle defects, burn-in reduction or elimination and test cost reduction through adaptive test

Creating Value Through Test

Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing before the ICs are shipped to the customer. In this paper, we show that techniques and tools used in the testing field can also be (re-)used to create value to (1) designers, (2) manufacturers, and (3) customers alike. First, we show how the test infrastructure can be used to detect, diagnose, and correct design errors in prototype silicon. Secondly, we discuss how test results are used to improve the manufacturing process and hence production yield. Finally, we present test technologies that enable systems of high reliability for safety-critical applications.