Branislav Kordic

PSTM: Python software transactional memory

TMs are becoming a mainstream parallel programming paradigm, but TM armed multicores are still not widely available and appropriate STMs for some popular languages like Python do not exist. These facts motivated as to develop our STM for Python (PSTM). In this paper, we firstly designed the PSTM architecture. Secondly, we implemented the PSTM prototype (PSTM-PT) which is based on Python Queue and Pipe mechanisms. Thirdly, we evaluated the PSTM-PT on the banking benchmarks and compared experimental results with previous theoretical results. The results presented in the paper are positive and stimulate follow-up work on PSTM.

DPM-PSTM: Dual-Port Memory Based Python Software Transactional Memory

Recently, hardware transactional memories (TMs) became available in some commercial multicore processors but due to its immaturity they are still not considered as a common feature available in processors, which provides researchers a chance to continue their work in the field of software TMs (STMs). This paper presents a novel STM design for Python (PSTM) based on a dual-port memory mechanism. The novel STM aims to mitigate overheads introduced by a message transferring mechanism used in the first version of PSTM, which is based on Queue and Pipe abstractions. Both versions are experimentally evaluated on Simple Bank program and simple performance benchmark. The PSTM version based on a dual-port memory mechanism achieves better performance in a case of intensive transaction (re)execution while in a first-take-successful transaction execution results of both PSTM versions are comparable. In the former case the PSTM version based on a dual-port memory mechanism achieves better results due to architecture advantages, i.e. reducing a message transfer overhead.

Work, Span, and Parallelism of Transactional Memory Programs

Recent developments indicate that after more than a decade of intensive pioneer work, both in academia and industry, transactional memory might finally become a standard part of the mainstream processors. Intel Haswell and IBM Blue Gene are first such processors indicating this trend. However, it is still not clear what would be the right performance metric and how it could be estimated and measured for a given TM program. This paper suggests that parallelism should be used as the performance metric and it proposes the method for estimating and measuring parallelism within a given TM program. In order to illustrate usage of the proposed method, we applied it to two realistic TM programs, namely Simple Bank and Race Bank. As the main result of our analysis we derived the lower and the upper bounds on parallelism for these two TM programs. Both programs have the same upper bound on parallelism, which varies from 2 to 14 when the number of read-write transactions increases from 100 to 1000, but Race Bank has better performance, because its lower bound on parallelism is constantly 1, whereas the lower bound on parallelism for Simple Bank is decreasing from 0.06 to 0.04.

Estimating transaction execution times for a software transactional memory

Over the last two decades, researchers developed many software, hardware, and hybrid Transactional Memories (TMs) with various APIs and semantics. However, reduced performance when exposed to high contention loads is still the major downside of all the TMs. Although many strategies and methods have been proposed, contention management and transaction scheduling still remains an open area of research. An important piece of unsolved contention management puzzle is plausible transaction execution time estimation. In this paper we proposed two methods for estimating transaction execution times, namely the method based on log-normal distribution and the method based on gamma distribution. Experimental results presented in this paper indicate that the method based on log-normal distribution has better estimation accuracy than the method based on gamma distribution. Even more importantly, the method based on log-normal distribution uses 10 times shorter sliding windows and its complexity is much lower than for the method based on gamma distribution, thus it is faster and requires less electrical power.

Parallel Processing of Multichannel Video Based on Multicore Architecture

Parallel processing and multi-core architectures are being accepted in all segments of industry caused by the need for better performance in real-time and non-real-time systems. This paper presents an implementation of parallel processing system for multichannel video on a multicore architecture using different building blocks. Black Screen Detection algorithm is used for digital image processing. The implemented system was validated by means of a particular case study. Experimentally obtained results are related to analysis of the system scalability, in terms of processing speed up as a function of the number of cores that participate in the processing. Also, due to the specific memory architecture, the influence of a ping-pong mechanism has been analyzed. Based on these results, the use of multi-core architecture for parallel processing to achieve significantly better performance of the target class of embedded systems is justified.

A method for creating the operational profile of TV/STB device to be used for statistical testing

This paper presents a comprehensive analysis of the integration process of statistical methodology for testing the system using tools like MaTeLo in Black-Box Testing system for automated testing. Through the specific example of testing a digital TV receiver, all the steps in testing process are analyzed: creation of devices operational profile (i.e. usage model) with the emphasis on determining the probability of transitions between states, automatic test case generation, test execution, and the analysis of results obtained by the MaTeLo tool.

A simulation of distributed STM

This paper presents an extension of the IaaS Cloud simulator CloudSim. Computational tasks are modeled in the form of a transaction on a transactional memory and communication between the data center is based on the Two-Phase Commit protocol. The model of the distributed STM prototype is implemented using the extended CloudSim simulator. The obtained results are as expected and in accordance with desired system behavior. The presented results are positive and they stimulate future work in development of distributed STM.

An approach to formal verification of python software transactional memory

Although Python is one of the most widely used programming languages, and it is a foundation for a variety of parallel and distributed computing frameworks, it still lacks an applicable and reliable software transactional memory. In this paper, we present an approach to formal verification of a Python Software Transactional Memory (PSTM) solution using UPPAAL tool. The aims are (i) to apply a formal verification process to a real STM implementation in order to derive a faithful STM model based on a PSTM design and (ii) to use developed PSTM model for automated machine-checked formal verification of core system properties such as safety and liveness using a model checker tool. Firstly, an architecture of PSTM solution is introduced. Secondly, formalization and a PSTM system model are analyzed. Finally, core PSTM systems properties are verified, namely safety, liveness, and reachability. Utilizing a UPPAALs model checker tool it is successfully verified that the PSTM system model satisfies each of the three formerly mentioned properties.

Test-Case Creation Framework for Touchscreen-Based Device Testing

This paper presents a framework for creation of test cases in a system for automated testing of touch screen-based devices. The system aims to automate the process of testing the devices on the final production line. The system uses a stimulation board which electrically stimulates touch screens, completely removing mechanical parts which induce lag and instability. Framework communicates with the stimulation board, sending signals which correspond to types of stimulation the board is supposed to achieve. Supported moves are: single touch, single release, multi touch, multi release, full release, line (swipe), multiline (pinch). The framework communicates with the stimulation board via the serial UART or Local Area Network interface. The testing is performed in following steps: (1) framework sends signals to the stimulation board, (2) board stimulates the device, (3) grabber captures the image of the screen on the device and (4) PC receives the image and verifies its correctness. The preliminary results show that the system is capable of reliable stimulation of touch screens which allows the creation of the complete system for automated testing.