Brent Keeth

Hybrid memory cube new DRAM architecture increases density and performance

Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density. Through-silicon vias (TSVs), 3D packaging and advanced CMOS performance enable a new approach to memory system architecture. Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.

A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM

A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V.

Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM

A 512Mb graphics DRAM device uses phase-tolerant read and write latency control to achieve 2Gb/s/pin GDDR3 and 2.5G/ps/pin GDDR4 operation. The IC is implemented in a 95nm 1.5V triple metal CMOS process.

A Self-Adaptive and PVT Insensitive Clock Distribution Network Design for High-Speed Memory Interfaces

A clock distribution network (CDN) insensitive to process, voltage, and temperature (PVT) variations is presented in this paper. Unlike a traditional source-synchronous interface, the CDN uses a current-mode logic (CML) divider and senseamp-based data receiver for data capture and deserialization. The proposed input path extends its operating range beyond 4Gb/s/pin without the need for retraining. A unique self-adaptive bias generator based on a Bandgap reference is also disclosed. Simulation data based on the CDN shows a 40% reduction in timing sensitivity for a 100mV supply voltage change and an 85°C temperature change at 4-Gb/s using a 3-metal, 50-nm DRAM process. Design considerations are also addressed based on power, performance, and complexity. Keywords-clock distribution network (CDN); current-mode logic (CML); Bandgap reference; deserializer; training; timing skew; voltage and temperature (VT) sensitivity; source synchronous; memory interface

Memory Interface Design for Hybrid Memory Cube (HMC)

Low-power and high-bandwidth communication can be established with TSV (through-silicon via) based Hybrid Memory Cube (HMC). This paper will describe a >1Tb/s bandwidth, sub 5 pJ/bit HMC memory interface fabricated using Micron 3-metal 3x nm CMOS technology. Design considerations and implementations for energy efficient I/O circuits, including TSV driver, sense-amp receiver and clocking strategy will be explored and discussed in detail. More than 10X of performance improvement can be achieved using the proposed technology.

A novel iterative method for approximating frequency response with equivalent pole/residues

Frequency domain modeling of interconnects has become the de facto standard for characterization in high-speed signal and power delivery systems. But time domain system level performance analysis calls for pole/residue representation followed by circuit level synthesis from the frequency domain sampled data model of interconnects. In this paper, a new iterative method that produces a set of equivalent poles and residues from discrete sampled frequency response data is proposed. Each iteration picks a few consecutive points from the given sampled response, identifies a local transfer function that matches their response and reduces error by subtracting the local transfer function. Two test cases, strip-line and package, are demonstrated. And results show that the proposed method has potential in fitting system frequency responses and has wide applications in signal and power integrity modeling and simulation of interconnect networks.

Keynote Address 2: “Hybrid memory cube: Achieving high performance and high reliability”

This keynote presentation will explore the genesis, architecture and construction of the Hybrid Memory Cube. The presentation will open with a discussion on how both technical and market forces led to the creation of HMC. This will be followed by a dive into the Gen 2 HMC design-detailing the design goals for the device and how manufacturability was a priority from day one. 3D integration is pivotal technology for HMC. As such, it will be explored in the context of key enablers and ongoing challenges. Finally, the presentation will discuss how HMC encompasses a variety of RAS features to improve manufacturability and to ensure long term device reliability.

Invited talk: The perfect memory storm

The 2000 Warner Brothers blockbuster movie “The Perfect Storm” depicted how a confluence of weather conditions in October 1991 combined to produce an epic killer storm in the North Atlantic. Caught in the storm was the swordfishing boat Andrea Gail. The boat and crew did not survive. Fast forwarding to 2014, the memory industry appears to be facing a perfect storm of its own. While survival of the industry is not at stake, it should nonetheless be an interesting period for anyone involved in producing or consuming memory. The forces contributing to this perfect memory storm include an apparent end to the evolutionary DDR roadmap, ongoing process scaling issues, industry consolidation, advances in emerging memory technology, and greater end market segmentation. This presentation will begin by briefly examining each of these issues and how they impact the path forward for memory. After that, the talk will focus on how this perfect storm might actually produce opportunities for technical innovation and result in a more differentiated product mix that would better serve the individual end markets. The Hybrid Memory Cube will be discussed within this context as a relevant and timely example.

The DRAM Array

This chapter begins a more detailed examination of standard DRAM array elements. This examination is necessary for a clear understanding of fundamental DRAM elements and how they are used in memory block construction. A common point of reference is required before considering the analysis of competing array architectures. Included in this chapter is a detailed discussion of mbits, array configurations, sense amplifier elements, and row decoder elements.