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Dive into the research topics where Troy A. Manning is active.

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Featured researches published by Troy A. Manning.


IEEE Micro | 2014

Near-Data Processing: Insights from a MICRO-46 Workshop

Rajeev Balasubramonian; Jichuan Chang; Troy A. Manning; Jaime H. Moreno; Richard C. Murphy; Ravi Nair; Steven Swanson

The cost of data movement in big-data systems motivates careful examination of near-data processing (NDP) frameworks. The concept of NDP was actively researched in the 1990s, but gained little commercial traction. After a decade-long dormancy, interest in this topic has spiked. A workshop on NDP was organized at MICRO-46 and was well attended. Given the interest, the organizers and keynote speakers have attempted to capture the key insights from the workshop into an article that can be widely disseminated. This article describes the many reasons why NDP is compelling today and identifies key upcoming challenges in realizing the potential of NDP.


IEEE Micro | 2017

In-Memory Intelligence

Tim Finkbeiner; Glen E. Hush; Troy D. Larsen; Perry V. Lea; John D. Leidel; Troy A. Manning

Recent activity in near-data processing has built or proposed systems that can exploit technologies such as 3D stacks, in-situ computing, or dataflow devices. However, little effort has been applied to exploit the natural parallelism and throughput of DRAM. This article details research from Micron Technology in the area of processing in memory as a form of memory-centric computing. In-Memory Intelligence (IMI) attempts to place a massive array of bit-serial computing elements on pitch with the memory array, as close to the information as possible. This contrasts with near-memory devices that rely on some form of storage but must communicate with that storage via a fast, low-latency interface. Initial simulations and models show stair-step improvements in performance and power for various applications. Such technology allows DRAM to provide functionality in a heterogeneous system to alleviate the pressures of the von-Neumann barrier.


Archive | 1998

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

David B. Gustavson; David V. James; Hans A. Wiggers; Peter B. Gillingham; Cormac M. O'Connell; Bruce Millar; Jean Crepeau; Kevin J. Ryan; Terry R. Lee; Brent Keeth; Troy A. Manning; Donald N. North; Desi Rhoden; Henry Stracovsky; Yoshikazu Morooka


Archive | 1999

Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same

Russel J. Baker; Troy A. Manning


Archive | 2002

Distributed write data drivers for burst access memories

Todd A. Merritt; Troy A. Manning


Archive | 2001

Delay-locked loop with binary-coupled capacitor

Troy A. Manning


Archive | 1996

Burst EDO memory device

Paul S. Zagar; Brett L. Williams; Troy A. Manning


Archive | 1998

Memory device with staggered data paths

Troy A. Manning


Archive | 1997

Multi-bank memory input/output line selection

Brent Keeth; Troy A. Manning


Archive | 1997

Method and apparatus for adjusting the timing of signals over fine and coarse ranges

Brent Keeth; Troy A. Manning

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Richard C. Murphy

Sandia National Laboratories

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