Brent Paulovicks

Video Analysis and Compression on the STI Cell Broadband Engine Processor

With increased concern for physical security, video surveillance is becoming an important business area. Similar camera-based system can also be used in such diverse applications as retail-store shopper motion analysis and casino behavioral policy monitoring. There are two aspects of video surveillance that require significant computing power: image analysis for detecting objects, and video compression for digital storage. The new STI CELL broadband engine (CBE) processor is an appealing platform for such applications because it incorporates 8 separate high-speed processing cores with an aggregate performance of 256Gflops. Moreover, this chip is the heart of the new Sony Playstation 3 and can be expected to be relatively inexpensive due to the high volume of production. In this paper we show how object detection and compression can be implemented on the CBE, discuss the difficulties encountered in porting the code, and provide performance results demonstrating significant speed-up

OpenCL and parallel primitives for digital TV applications

Open Computing Language®(OpenCL®), which is created to support H. Yeo parallel programming of heterogeneous multicore-processor systems, has a very large potential for high-performance computing and consumer electronics since it provides application programming interfaces (APIs) to help make a portable code that runs across multiple devices. OpenCL is still under development, and it is not clear whether OpenCL has any advantages over other frameworks aside from portability. The purpose of our project was to define evaluation criteria, empirically evaluate OpenCL as a programming framework using evaluation criteria (e.g., performance, productivity, and portability criteria), define and implement parallel primitives in OpenCL, and demonstrate how the use of the implemented parallel primitives can have benefits for our target applications. Parallel primitive library APIs are defined to implement parallel algorithms in OpenCL, and a set of data- and task-parallel primitives is implemented and incorporated in the target applications. Multicore central processing units, the Cell Broadband Engine®(Cell/B.E.®), and graphics processing units are used as target platforms, and digital TV applications are used to evaluate usefulness of OpenCL. Preliminary results show that parallel primitives can be one of the ways to improve application performance and programmer productivity with respect to OpenCL while still maintaining software portability.

High performance computing of line of sight viewshed

In this paper we present our recent research and development work for multicore computing of Line of Sight (LoS) on the Cell Broadband Engine (CBE) processors. LoS can be found in many applications where real-time high performance computing is required. We will describe an efficient LoS multi-core parallel computing algorithm, including the data partition and computation load allocation strategies to fully utilize the CBEs computational resources for efficient LoS viewshed parallel computing. In addition, we will also illustrate a successive fast transpose algorithm to prepare the input data for efficient Single-Instruction-Multiple-Data (SIMD) operations. Furthermore, we describe the data input and output (I/O) management scheme to reduce the (I/O) latency in Direct-Memory-Access (DMA) data fetching and storing operations. The performance evaluation of our LoS viewshed computing scheme over an area of interest (AOI) with more than 4.19 million points has shown that our parallel computing algorithm on CBE takes less than 25.5 ms, which is several orders of magnitude faster than the available commercial systems.

Parallel implementation of external sort and join operations on a multi-core network-optimized system on a chip

In a commercial Relational Database Management System (RDBMS), sort and join are the most demanding operations, and it is quite beneficial to improve the performance of external sort and external join algorithms that handle large input data sizes. This paper proposes parallel implementations of multithreaded external sort and external hash join algorithms to accelerate IBM DB2, one of leading RDBMSs, using an IBM Power Edge of Network (IBM PowerEN™) Peripheral Component Interconnect Express (PCIe) card as an accelerator. The preliminary results show that the proposed parallel implementation of the algorithms on PowerEN™ PCIe card can speed up the DB2 sort and join performance about two times.

Data-at-rest security for spark

Apache Spark enables fast computations and greatly accelerates analytics applications by efficiently utilizing the main memory and caching data for later use. At its core Apache Spark uses data structures called RDDs (Resilient Distributed Datasets) to give a unified view to the distributed data. However, the data represented in the RDDs remain unencrypted which can result in leakage of confidential data produced or processed by applications. Apache Spark persists (unencrypted) RDDs to the disk storage under various circumstances including but not limited to caching, RDD checkpointing and data spill during the data shuffling operations, etc. This lack of security makes Apache Spark unsuitable for processing of sensitive information that should be secured at all times. Moreover, RDDs stored in the main memory are prone to main-memory attacks such as RAM-scrapping. In this paper, we propose and develop solutions to fill-up such security lapses in the current Apache Spark framework. We present three different approaches to incorporate security in the Apache Spark framework. These approaches are designed to limit the exposure of unencrypted data during data processing, caching and data spill to disk. We use combination of cryptographic splitting and encryption to secure data stored and spilled by Apache Spark, both to the disk as well as to the main memory. Our approaches provide strong security by incorporating combination of Information Dispersal Algorithm (IDA) and Shamirs Perfect Secret Sharing (PSS). Extensive experimentation show that with appropriately chosen parameters our security approaches provide high security at a performance penalty between 10%–25%.

Digital video surveillance platform based on cell processor and H.264 video compression

We analyze challenges in the current approaches to digital video surveillance solutions, both technically and financially. We propose a Cell Processor based digital video surveillance platform to overcome those challenges and address ever growing needs in enterprise class surveillance solutions capable of addressing multiple thousands camera installations. To improve the compression efficiency we have chosen H.264 video compression algorithm which outperforms all standard video compression schemes as of today.

Cell blade based H.264 video encoding engine for large scale video surveillance applications

Video surveillance has become one of the most important tools for public safety and security. In this paper, we present our new work on developing efficient parallel computing algorithms and schemes for implementing H.264 video encoder engine on Cell Broadband Engine (CBE) blade for high performance large scale video surveillance applications. Extending our previous work on H.264 video encoding on CBE, we have developed new parallel computing schemes in computational load partition, dynamic task scheduling, motion estimation, and mode selection. We partition the intensive H.264 video encoding computation load into four major functional modules, namely, the pre-processing module, the motion estimation module, the mode selection and transform/quantization module, and the Context Adaptive Binary Arithmetic Coding (CABAC) module. The task scheduler dynamically assigns a waiting computing task to a SPE as soon as it becomes available. Our new implementation has achieved more than 5X performance improvement to encode 32 standard-definition (SD 720x480 pixel resolution) H.264 video streams simultaneously at 30 frames per second with one Cell Blade that consists of 16 Synergistic Processor Elements (SPEs) and two control Power Processor Elements (PPEs) or 448 SD channels of H.264 video streams on a single chassis Cell Blade Center with 14 Cell Blades.