Brian C. Richards

Chisel: constructing hardware in a Scala embedded language

In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to map to either FPGAs or to a standard ASIC flow for synthesis. This paper presents Chisel, its embedding in Scala, hardware examples, and results for C++ simulation, Verilog emulation and ASIC synthesis.

Participatory design of an orientation aid for amnesics

We present the participatory design and evaluation of an orientation aid for individuals who have anterograde amnesia. Our design team included six amnesics who have extreme difficulty storing new memories. We describe the methods we used to enable the participation of individuals with such severe cognitive impairments. Through this process, we have conceived, designed, and developed the OrientingTool, a software application for Personal Digital Assistants that can be used by amnesics to orient themselves when feeling lost or disoriented. Two complementary studies were conducted to evaluate the effectiveness of this tool in ecologically valid contexts. Our findings suggest that the OrientingTool can improve an amnesics independence and confidence in managing situations when disoriented, and that participatory design may be productively used with participants who have significant cognitive disabilities.

Rapid design and analysis of communication systems using the BEE hardware emulation environment

This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and design environment for communication and digital signal processing (DSP) systems, consisting of four multi-FPGA based processing units, each capable of emulating 10 million ASIC (application specific integrated circuits) equivalent gates at an overall system clock rate up to 60 MHz. This translates to over 600 billion 16 bit additions (operations) per second on one unit. An integrated software design flow enables the users to specify the design using a data-flow diagram, then automatically generates both the FPGA implementation for real-time rapid prototyping and a cycle-accurate, bit-true, and functionally equivalent ASIC implementation. For system-level design, the BEE hardware and software support rapid design turn-around and early performance analysis, without full synthesis or hardware mapping, from the high-level design entry. A case study detailing a turbo-decoder explains how the processing capability of the emulator can be utilized to verify a design using one billion input vectors with a speed-up factor exceeding 106 over equivalent software simulation methods.

Participatory design with individuals who have amnesia

We present experiences and insights into participatory design with individuals who have anterograde amnesia and therefore have extreme difficulty storing new memories. We discuss our design of the design process, and present a set of techniques used to support memory during and between design sessions. From this experience, we identify cognitive assumptions of participatory design that break down when working with amnestics. We generalize these ideas into an analytical framework for researchers and practitioners who intend to use participatory design with persons having various kinds of cognitive impairments. We illustrate the framework by analyzing a cognitive deficit unrelated to memory that we encountered, and an unanticipated benefit from what at first appeared to be a liability in working with this design team.

Implementation of BEE: a real-time large-scale hardware emulation engine

This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated Circuits) equivalent gates. Attainable system operation frequency can exceed 60 MHz, and the system throughput has been empirically verified to achieve 600 billion 16-bit additions per second. The emulator is custom designed to maximize the performance and resource utilization for a range of telecommunication and digital signal processing applications. With its high-speed interconnect architecture and large external I/O bandwidth, the emulator excels in prototyping real-time systems that have strict timing, logic capacity, and data rate requirements. Our development efforts are guided by such ongoing projects as ultra-wide band (UWB) and multi-channel-multi-antenna (MCMA) radio systems research.

A prototype user interface for a mobile multimedia terminal

We have shown a prototype user interface for the InfoPad, a portable terminal with multi-modal input and multimedia output. We believe that many of the people who could benefit from inexpensive, portable, networked terminals are not computer experts, and we are therefore designing the InfoPad and its user interface to be more like a notebook than a workstation. The InfoPad’s main features are: ● Portabilityy ●Continuous network connectivity using a highbandwidth radio link ● Pen input with handwriting recognition ● Audio input with speech recognition ● Full-motion video playback with synchronized audio The InfoPad’s unique input and output characteristics offer challenges and opportunities for user interface design. We are prototyping applications and user interfaces to explore how handwriting and voice recognition may best be used together. We believe that the lessons we will learn can be applied to other multi-modal platforms.

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

ASIC Design and Verification in an FPGA Environment

A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4times4 MIMO signal processing.

Designing BEE: a hardware emulation engine for signal processing in low-power wireless applications

This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.