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Dive into the research topics where Brian Cronquist is active.

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Featured researches published by Brian Cronquist.


ieee international d systems integration conference | 2013

Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC

Bipin Rajendran; Albert K. Henning; Brian Cronquist; Zvi Or-Bach

Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.


ieee soi 3d subthreshold microelectronics technology unified conference | 2015

Modified ELTRAN® — A game changer for Monolithic 3D

Zvi Or-Bach; Brian Cronquist; Zeev Wurman; Israel Beinglass; Albert K. Henning

It is well recognized that dimensional scaling has reached its diminishing return phase and the industry is now looking to monolithic 3D to be the future technology driver. This was clearly voiced in the Qualcomm keynote at DAC 2014 and follow-on presentation at ISPD 2015. This paper will present a novel use of the ELTRAN® process developed by Canon Inc. about 20 years ago primarily for SOI applications. Using ELTRAN techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change the current frontline fab process. This flow is further simplified and could be integrated with the game changing monolithic 3D flow introduced last year which leverages the emerging precision bonders, such as EVGs Gemini® XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge. In addition, this game-changer breakthrough offers a very cost competitive flow.


ieee soi 3d subthreshold microelectronics technology unified conference | 2013

Thermal considerations for monolithic integration of three-dimensional integrated circuits

Albert K. Henning; B. Rajendran; Brian Cronquist; Zvi Or-Bach

A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.


Archive | 2010

System comprising a semiconductor device and structure

Zvi Or-Bach; Brian Cronquist; Israel Beinglass; Jan Lodewijk de Jong; Deepak C. Sekar; Zeev Wurman


Archive | 2012

Semiconductor device and structure

Zvi Or-Bach; Brian Cronquist


Archive | 2011

Method for fabrication of a semiconductor device and structure

Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist; Israel Beinglass; Jan Lodewijk de Jong


Archive | 2012

Novel semiconductor device and structure

Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist


Archive | 2013

3D semiconductor device and structure

Zvi Or-Bach; Brian Cronquist; Deepak C. Sekar


Archive | 2011

Method of constructing a semiconductor device and structure

Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist; Israel Beinglass; Zeev Wurman; Paul Lim


Archive | 2012

Novel semiconductor system and device

Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist; Zeev Wurman

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Bipin Rajendran

New Jersey Institute of Technology

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Hui Geng

University of Science and Technology

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Luke Maresca

University of Science and Technology

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Yiyu Shi

University of Science and Technology

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