Brian Cronquist
Rice University
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Publication
Featured researches published by Brian Cronquist.
ieee international d systems integration conference | 2013
Bipin Rajendran; Albert K. Henning; Brian Cronquist; Zvi Or-Bach
Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.
ieee soi 3d subthreshold microelectronics technology unified conference | 2015
Zvi Or-Bach; Brian Cronquist; Zeev Wurman; Israel Beinglass; Albert K. Henning
It is well recognized that dimensional scaling has reached its diminishing return phase and the industry is now looking to monolithic 3D to be the future technology driver. This was clearly voiced in the Qualcomm keynote at DAC 2014 and follow-on presentation at ISPD 2015. This paper will present a novel use of the ELTRAN® process developed by Canon Inc. about 20 years ago primarily for SOI applications. Using ELTRAN techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change the current frontline fab process. This flow is further simplified and could be integrated with the game changing monolithic 3D flow introduced last year which leverages the emerging precision bonders, such as EVGs Gemini® XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge. In addition, this game-changer breakthrough offers a very cost competitive flow.
ieee soi 3d subthreshold microelectronics technology unified conference | 2013
Albert K. Henning; B. Rajendran; Brian Cronquist; Zvi Or-Bach
A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.
Archive | 2010
Zvi Or-Bach; Brian Cronquist; Israel Beinglass; Jan Lodewijk de Jong; Deepak C. Sekar; Zeev Wurman
Archive | 2012
Zvi Or-Bach; Brian Cronquist
Archive | 2011
Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist; Israel Beinglass; Jan Lodewijk de Jong
Archive | 2012
Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist
Archive | 2013
Zvi Or-Bach; Brian Cronquist; Deepak C. Sekar
Archive | 2011
Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist; Israel Beinglass; Zeev Wurman; Paul Lim
Archive | 2012
Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist; Zeev Wurman