Zvi Or-Bach

A novel Bi-stable 1-transistor SRAM for high density embedded applications

A 1-transistor SRAM on bulk substrate is presented. The device is fabricated in 28 nm foundry baseline process with an additional buried N-well (BNWL) implant. The unit cell consists of a lateral MOS for memory access operations and intrinsic vertical open-base bipolar structures for self-latch function. The bit cell operation and the disturb immunity are verified at high temperature. Using 28 nm design rules, a unit cell size of 0.025 μm2 is achieved, offering 80% cell size reduction over 6T-SRAM and providing comparable power and performance.

A CMOS-compatible boosted transistor having >2× drive current and low leakage current

A novel boosted MOS structure with buried n-well current booster providing >2× higher drive current and low off current is experimentally demonstrated on 28 nm bulk silicon technology. TCAD analysis is performed to investigate the boosting mechanism as well as to demonstrate scalability to 7 nm FinFET technology. Constant bias applied to the booster terminal results in a gate voltage controlled body current source intrinsic vertical BJT that only turns on at high gate voltage. The body current then amplifies lateral BJT current. The inherent vertical and lateral BJTs are automatically turned off at low gate voltage, maintaining low off-state current.