Brian D. Philofsky

Stacked Silicon Interconnect (SSI)

A growing trend in the semiconductor market is to gravitate toward 2.5D and 3D technologies as a way to extend and improve the growth and integration path that Moore’s law has paved for more than 50 years. Xilinx has been a forerunner into this emerging technology entering into this foray in 2011 with the public introduction of the Xilinx XC7V2000T device utilizing four active die on a passive interposer creating not only the largest FPGA of the time but one of the first commercially available examples of this new technology. Since the introduction of that device, several other devices have followed and now are becoming a more mainstream means to realize large, high-performance devices to address some of the most demanding FPGA designs. Due to the sheer size and unique construction of these devices, a new approach to design should be considered in order to facilitate design entry, implementation, and closure.

Best engineering practice for thermal characterization of stacked dice FPGA devices

This paper presents a couple of new methodologies regarding package characterization. An important shortcoming of the JEDEC methodology for single-die packages is that it does not account for the real-world scenario of a packages boundary condition. A new methodology is proposed to overcome this shortcoming by accounting for typical PCB conductivities and heatsink attachments to packages. The second methodology, presented in the paper, shows a better way to develop DELPHI-based boundary condition independent compact thermal models for 2.5D packages with multiple dies mounted on an interposer. This methodology, based on DELPHI-based techniques, accounts for the interaction between the multiple dies in a package. This is done by modifying the resistors generated from the optimization process. A number of verification cases show good fidelity of the compact thermal model to the detailed model.

A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applications

Silicon Interconnect Technology (SSIT) enables superior feature integration beyond what is possible in monolithic technology with only a Moores Law feature shrink as well as heterogeneous feature integration of disparate dice (e.g. memories, RF DAC/ADCs, optical interfaces, customer ASICs etc.). In a Telecom environment, this superior feature density enables new applications, but also presents higher thermal density to the Thermal Engineer. To properly utilize these benefits, a Thermal Engineer must take a holistic approach to thermal architecture that simultaneously addresses system goals of Cost, Performance, Weight, Size, Power and Performance. This paper will discuss the critical parameters which impact thermal architecture, followed by Challenges in Indoor and Outdoor Telecom Systems from device and system perspectives and finally will show the impact of combining network utilization and heterogeneous load in the users environment.