Gamal Refai-Ahmed

Product-level reliability estimator with budget-based reliability management in 16nm technology

Product-level Reliability Estimator (PLRE) has been built for 20nm technology product. With PLRE, users can estimate failure rate of the chip with various use conditions. EDA tools are used to estimate each blocks reliability budget, in terms of effective area for TDDB and effective number for EM which are to be used in building PLRE. Budget-based reliability check procedure was explained, which let designers have more room for reliability to get better circuit performance. Results of PLRE show that EM and MOL TDDB can be an actual risk in specific use condition.

Systematic Approach to Design High Power FPGA Package for Current-Carrying Capability

This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution and to calculate accumulated failure rates from an entire substrate including BGA ball, micro-via and plated through hole. The approach reported here allows lifetime calculation from the progressive failure of individual BGA over the different time span. In the end, we apply the methodology to a 200A high power design achieved with the most efficient ball count that meets lifetime specification.

High power FPGA package design to maximize current-carrying capability

The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design for optimal current distribution directly to failure rate as a result of electro-migration (EM) in stated lifetime. Secondly, a specific design case is analyzed with the new method to show how BGA pin pattern can impact maximal current carrying capability.

Best engineering practice for thermal characterization of stacked dice FPGA devices

This paper presents a couple of new methodologies regarding package characterization. An important shortcoming of the JEDEC methodology for single-die packages is that it does not account for the real-world scenario of a packages boundary condition. A new methodology is proposed to overcome this shortcoming by accounting for typical PCB conductivities and heatsink attachments to packages. The second methodology, presented in the paper, shows a better way to develop DELPHI-based boundary condition independent compact thermal models for 2.5D packages with multiple dies mounted on an interposer. This methodology, based on DELPHI-based techniques, accounts for the interaction between the multiple dies in a package. This is done by modifying the resistors generated from the optimization process. A number of verification cases show good fidelity of the compact thermal model to the detailed model.

A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applications

Silicon Interconnect Technology (SSIT) enables superior feature integration beyond what is possible in monolithic technology with only a Moores Law feature shrink as well as heterogeneous feature integration of disparate dice (e.g. memories, RF DAC/ADCs, optical interfaces, customer ASICs etc.). In a Telecom environment, this superior feature density enables new applications, but also presents higher thermal density to the Thermal Engineer. To properly utilize these benefits, a Thermal Engineer must take a holistic approach to thermal architecture that simultaneously addresses system goals of Cost, Performance, Weight, Size, Power and Performance. This paper will discuss the critical parameters which impact thermal architecture, followed by Challenges in Indoor and Outdoor Telecom Systems from device and system perspectives and finally will show the impact of combining network utilization and heterogeneous load in the users environment.