Brian Fitzgibbon

Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity

In mixed-signal systems, nonlinear distortion due to nonideal analog circuitry can act on quantized digital sequences, giving rise to spurious tones. In this brief, generation of spurious tones in digital delta-sigma modulators, followed by memoryless nonlinearity, is investigated. Inherent modulator periodicity that persists even with the use of least-significant-bit dither is identified.

Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

In this two-part paper, a design methodology for bus-splitting digital delta-sigma modulators (DDSMs) is presented. The design methodology is based on error masking and is applied to both ditherless and dithered DDSMs with constant and sinusoidal inputs. Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations and experimental results confirm the theoretical predictions. Part I addresses ditherless MASH DDSMs with constant inputs; Part II focuses on DDSMs with dither and sinusoidal inputs.

Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither

Abstract Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This happens when the input is constant or periodic. Pseudorandom dither generators are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can have limited effectiveness. This paper addresses the fundamental limitations of using pseudorandom dither signals that are inherently periodic. We clarify some common misunderstandings in the DDSM literature. We present rigorous mathematical analysis, case studies to illustrate the issues, and insights which can prove useful in design.

Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs

Higher order error feedback modulators are analyzed mathematically to investigate their periodic behavior. We derive nonlinear equations governing the systems and evaluate the quantizer error equations to determine optimum initial conditions from which maximum cycle lengths can be achieved.

A Spur-Free MASH DDSM With High-Order Filtered Dither

A novel dithered multistage noise shaping (MASH) digital delta-sigma modulator (DDSM) that produces a spur-free output spectrum is presented. The order of the least significant bit (LSB) dither shaping can be increased to that of the modulator, without producing spurious tones. Theoretical results prove that the quantization noise is asymptotically white and uncorrelated with the input; this is corroborated by behavioral simulations.

Spurious tones in digital delta sigma modulators with pseudorandom dither

Pseudorandom dither generators are widely used to break up periodic cycles in digital delta sigma modulators in order to minimize spurious tones produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can have limited effectiveness. This paper identifies some limitations of using pseudorandom dither signals that are inherently periodic.

A spur-free MASH digital delta-sigma modulator with higher order shaped dither

This paper presents a novel design for a Digital Delta Sigma Modulator (DDSM) which produces a spur-free spectrum for all constant inputs with higher order shaped additive LSB dither. We can increase the order of noise shaping of the applied dither to that of the modulator without any spurious tones appearing in the spectrum. The result is confirmed by simulation.

A novel implementation of dithered digital delta-sigma modulators via bus-splitting

This paper presents a design methodology for dithered bus-splitting Multi stAge noise SHaping (MASH) digital delta-sigma modulators (DDSMs). Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations are presented which confirm the theoretical predictions.

0.3–4.3 GHz Frequency-Accurate Fractional-

If the modulus of the digital delta-sigma modulator (DΔΣM) in a fractional- N frequency synthesizer is a power of two, then the output frequency is constrained to be a rational multiple of the phase detector frequency (fPD), where the denominator of the rational multiplier is a power of two. If the required output frequency is not related to fPD in this way, one is forced to approximate the ratio by using a small programmable modulus DΔΣM or a very large power-of-two modulus. Both of these solutions involve additional hardware. Furthermore, the programmable modulus solution can suffer from spurs, while the large power of two lacks accuracy. This paper presents a new solution, based on mixed-radix algebra, where the required ratio is formed by combining two different moduli. The programmable modulus solves the accuracy problem, while the large power-of-two modulus minimizes the spur content. In addition, the phase detector can be clocked at high speed. This paper explains the theoretical foundations of the method, elaborates a design methodology, and presents measured results for an 0.18 μm SiGe BiCMOS prototype.

N

A mathematical analysis is performed to investigate the periodic behavior of Multi stAge noise SHaping (MASH) Digital Delta-Sigma Modulators (DDSMs). The analysis is performed on fourth- and fifth-order MASH DDSMs with an odd initial condition on the first stage and all other states initially zeroed. We prove that the maximum cycle length for the fourth- and fifth-order MASH DDSM is 2N+2 where N is the wordlength of the modulator. In the case of fourth-order modulators, the maximum cycle length can be achieved when odd digital inputs are applied. In the case of fifth-order modulators, the cycle length is 2N+2 for all digital inputs.