Brian M. Sutton

Stochastic p -Bits for Invertible Logic

Conventional logic and memory devices are built out of deterministic units such as transistors, or magnets with energy barriers in excess of 40-60 kT. We show that stochastic units, p-bits, can be interconnected to create robust correlations that implement Boolean functions with impressive accuracy, comparable to standard circuits. Also they are invertible, a unique property that is absent in digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among possible inputs consistent with that output. We present an implementation of an invertible gate to bring out the key role of a three-terminal building block to enable the construction of correlated p-bit networks. The results for this implementation agree well with those from a universal model, showing that p-bits need not be magnet-based: any three-terminal tunable random bit generator should be suitable. We present an algorithm for designing a Boltzmann machine (BM) with symmetric connections that implements a given truth table. We then show how BM Full Adders can be interconnected in a partially directed manner to implement large operations such as 32-bit addition. Hundreds of p-bits get precisely correlated such that the correct answer out of 2^33 possibilities can be extracted by looking at the mode of a number of time samples. With perfect directivity a small number of samples is enough, while for less directed connections more samples are needed, but even in the former case invertibility is largely preserved. This combination of accuracy and invertibility is enabled by the hybrid design that uses bidirectional units to construct circuits with partially directed connections. We establish this result with examples including a 4-bit multiplier which in inverted mode functions as a factorizer.

Spin switches for compact implementation of neuron and synapse

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltages that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.