Behtash Behin-Aein

A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies

The development of a scalable and user-friendly SPICE model is a key aspect of exploring the potential of spin-transfer torque MRAM (STT-MRAM). A self-contained magnetic tunnel junction (MTJ) SPICE model is proposed in this work which can reproduce realistic MTJ characteristics based on user-defined input parameters such as the free layers length, width, and thickness. Using the propose model, scalability studies of both in-plane and perpendicular MTJs can be performed across different technology nodes with minimal effort, which differentiates this model from most previously reported models.

Computing with spins and magnets

The possible use of spin and magnets in place of charge and capacitors to store and process information is well known. Magnetic tunnel junctions are being widely investigated and developed for magnetic random access memories. These are two terminal devices that change their resistance based on switchable magnetization of magnetic materials. They utilize the interaction between electron spin and magnets to read information from the magnets and write onto them. Such advances in memory devices could also translate into a new class of logic devices that offer the advantage of nonvolatile and reconfigurable information processing over transistors. Logic devices having a transistor-like gain and directionality could be used to build integrated circuits without the need for transistor-based amplifiers and clocks at every stage. We review device characteristics and basic logic gates that compute with spins and magnets from the mesoscopic to the atomic scale, as well as materials, integration, and fabrication challenges and methods.

Spin switches for compact implementation of neuron and synapse

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltages that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.

Tunneling and Short Channel Effects in Ultrascaled InGaAs Double Gate MOSFETs

Full-band quantum transport simulations are performed to study the scaling of InGaAs MOSFETs. Short-channel effects evoke severe performance degradation in InGaAs MOSFETs and the tunneling leakage further deteriorates their performances. Reducing the body width is shown to suppress the short channel effects. Doping densities show big impacts on device performances. With inhomogeneous doping InGaAs could outperform Si at gate lengths below 15 nm with 5-nm body width. The density of state bottleneck does not affect InGaAs in simulated devices at 0.5 V supply voltage. At the ultrascaled dimensions the full band simulations are essential to capture strong nonparabolic dispersion. Comparison with a multivalley effective mass model shows that the population of higher conduction band valleys contributes to the total current at thin body widths.

Modeling circuits with spins and magnets for all-spin logic

This talk will summarize our work in the last three years exploring the possibility of spin-magnet circuits that utilize two key recent advances, namely (1) spin valve (SV) devices demonstrating spin injection into metals and semiconductors from magnetic contacts and (2) spin transfer torque (STT) devices demonstrating the switching of magnets by the injected spins. Utilizing an experimentally benchmarked model describing these phenomena we have shown the possibility of Boolean all-spin logic (ASL) circuits with intrinsic directionality or with directionality enforced through STT based Bennett clocking. We also discuss probabilistic ASL circuits and summarize the modeling framework that we have developed for the analysis of generic spin-magnet circuits.

Fokker—Planck Study of Parameter Dependence on Write Error Slope in Spin-Torque Switching

This paper analyzes write errors in spin torque switching due to thermal fluctuations in a system with Perpendicular Magnetic Anisotropy (PMA). Prior analytical and numerical methods are summarized, a physics based Fokker-Planck Equation (FPE) chosen for its computational efficiency and broad applicability to all switching regimes. The relation between write error slope and material parameters is discussed in detail to enable better device engineering and optimization. Finally a 2D FPE tool is demonstrated that extends the applicability of FPE to write error in non PMA systems with built-in asymmetry. Keywords—PMA, spin transfer torque, 2D Fokker-Planck, write error rate.This paper analyzes write errors in spin-torque switching due to thermal fluctuations in a system with perpendicular magnetic anisotropy. Prior analytical and numerical methods are summarized; a physics-based general 2-D Fokker-Planck equation (FPE) is solved numerically. Due to its computational efficiency and broad applicability to all switching regimes and system symmetries, the 2-D FPE has been used to study the relation between write error slope and material parameters as well as some emerging switching schemes.