Brian Pratt

A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs

With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. Triple-modular redundancy (TMR) is a common fault mitigation technique for FPGAs and has been successfully demonstrated by several organizations. This technique, however, requires significant hardware resources. This paper evaluates three additional mitigation techniques and compares them to TMR. These include quadded logic, state machine encoding, and temporal redundancy, all well-known techniques in custom circuit technologies. Each of these techniques are compared to TMR in both area cost and fault tolerance. The results from this paper suggest that none of these techniques provides greater reliability and often require more resources than TMR.

SEU-induced persistent error propagation in FPGAs

This paper introduces a new way to characterize the dynamic single-event upset (SEU) cross section of an FPGA design in terms of its persistent and nonpersistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the nonpersistent cross section causes a temporary interruption of service. These cross sections have been measured for several designs using fault-injection and proton testing. Some FPGA applications may realize increased reliability at lower costs by focusing SEU mitigation on just the persistent cross section.

SRAM FPGA Reliability Analysis for Harsh Radiation Environments

This paper investigates the viability of deploying SRAM-based FPGAs into harsh Earth-orbit environments. A reliability model is presented for estimating the MTTF of SRAM FPGA designs in specific orbits and orbit conditions. The model requires orbit- and condition-specific SEU rates and design-specific estimates of the probability of failure during a single scrubbing period. Probability of failure estimates are reported for several FPGA designs from both fault-injection and accelerator experiments. The model also includes a method for estimating composite mean time to failure (MTTF) that incorporates all orbit conditions over a solar cycle. Despite using pessimistic assumptions, the results from this model suggest that SRAM FPGA designs protected by TMR and scrubbing operate very reliably in a LEO orbit and surprisingly well in ¿harsh¿ orbits.

Fine-Grain SEU Mitigation for FPGAs Using Partial TMR

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally at a very fine level until the available resources are utilized. Thus the tool aims to gives the maximum reliability gain for the specified area cost.

A Test Methodology for Determining Space Readiness of Xilinx SRAM-Based FPGA Devices and Designs

Using reconfigurable static random access memory (SRAM)-based field-programmable gate arrays (FPGAs) for space-based computation has been a very active area of research for the past decade. Because these commercially available devices are only radiation tolerant in terms of total ionizing dose and single-event latchup, these devices must be qualified for other types of single-event effects to be used in spacecraft. Furthermore, mission requirements often dictate the need to do radiation experiments on the FPGA user circuit. Because both the circuit and the circuits state are stored in memory that is susceptible to single-event upsets, both could be altered by the harsh space radiation environment. Both the circuit and the circuits state can be protected by triple-modular redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe both device-level static testing and user circuit dynamic testing, including a three-tiered methodology for testing FPGA user designs for space readiness.

An Automated Approach to Estimating Hardness Assurance Issues in Triple-Modular Redundancy Circuits in Xilinx FPGAs

The Xilinx Virtex family of static random access memory (SRAM) based field programmable gate array (FPGA) devices have made inroads into space-based computational platforms over the past decade. These devices are well-suited for digital signal processing (DSP) algorithms that are often used on orbit, providing the speedup of custom hardware without the cost of fabricating an application-specific integrated circuit (ASIC). SRAM FPGAs store the circuit in radiation-tolerant SRAM and SEUs can affect both the circuit functionality and the circuit state. Triple-modular redundancy (TMR) can be used to mask SEUs so that malfunctioning circuitry will not affect the output data. Unfortunately, applying TMR to a user circuit is difficult and unprotected cross-section is possible due to problems with the circuit design, device constraints, or the implementation of the user circuit on the FPGA. Given the complexity of these designs, estimating hardness assurance issues is not simple. This paper will present a tool, called the scalable tool for the analysis of reliable circuits (STARC), that can automatically estimate unprotected cross-section and other hardness assurance issues for TMR-protected circuits.

The Cibola Flight Experiment

Over the past 15 years many organizations have researched the use of Static-Random Access Memory (SRAM)-based Field-Programmable Gate Arrays (FPGAs) in space. Although the components can provide a performance improvement over radiation-hardened processing components, random soft errors can occur from the naturally occurring space radiation environment. Many organizations have been developing methods for characterizing, emulating, and simulating radiation-induced events; mitigating and removing radiation-induced computational errors; and designing fault-tolerant reconfigurable spacecraft. Los Alamos National Laboratory has fielded one of the longest space-based FPGAs experiments, called the Cibola Flight Experiment (CFE), using Xilinx Virtex FPGAs. CFE has successfully deployed commercial SRAM FPGAs into a low-Earth orbit with Single-Event Upset (SEU) mitigation and was able to exploit effectively the reconfigurability and customization of FPGAs in a harsh radiation environment. Although older than current state-of-the-art FPGAs, these same concepts are used to deploy newer FPGA-based space systems since the launch of the CFE satellite and will continue to be useful for newer systems. In this article, we present how the system was designed to be fault tolerant, prelaunch predictions of expected on-orbit behaviors, and on-orbit results.

Reliable Communications Using FPGAs in High-Radiation Environments - Part I: Characterization

Reconfigurable radios implemented on FPGAs operating in high-radiation environments are subject to single-event- upsets (SEUs). The traditional mitigation method of applying triple modular redundancy (TMR) to the entire design does not have to be used in this application. This is because the majority of the SEUs impact the overall performance (measured by bit error rate) in the same way additive noise does. The results of this paper show which sections must be protected from SEUs and provide a guide for the bit error rate performance versus FPGA area tradeoff as a function of SEU mitigation.

Noise impact of single-event upsets on an FPGA-based digital filter

Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in a digital filter, showing that many SEUs in a digital communications system cause effects that could be considered noise rather than circuit failure. Since DSP and digital communications applications are designed to withstand certain types of noise, SEU mitigation techniques that are less costly than TMR may be applicable. This could result in large savings in area and power when implementing a reliable system. Our experiments show that, of the SEUs that affected the digital filter with a 20 dB SNR input signal, less than 14% caused an SNR loss of more than 1 dB at the output.

Reduced-precision redundancy on FPGAs

Reduced-precision redundancy (RPR) has been shown to be a viable alternative to triple modular redundancy (TMR) for digital circuits. This paper builds on previous research by offering a detailed analysis of the implementation of RPR on FPGAs to improve reliability in soft error environments. Example implementations and fault injection experiments demonstrate the cost and benefits of RPR, showing how RPR can be used to improve the failure rate by up to 200 times over an unmitigated system at costs less than half that of TMR. A novel method is also presented for improving the error-masking ability of RPR by up to 5 times at no additional hardware cost under certain conditions. This research shows RPR to be a very flexible soft error mitigation technique and offers insight into its application on FPGAs.