Brian R. Harkness

Photopatternable thin films from silyl hydride containing silicone resins and photobase generators

The photopatternability of various silyl hydride containing organosilicone resins containing the photobase generators N-methylnifedipine or O-(2-nitrobenzyl)-N-octyl carbamate have been examined, with the goal of identifying potential photopatternable compositions with high thermal stability after cure. Two different categories of silicone resins have been prepared from combinations of diphenylsiloxane and methyl and hydrogen silsesquioxane units and a combination of phenyl and hydrogen silsesquioxane monomer units. The photobase generators were incorporated into these resins at concentrations up to 10 weight percent. UV-irradiation of micrometer thick silicone resin-photobase films through a photomask, under an air atmosphere, yielded micrometer scale features after development. Photopatternable compositions have been identified with photosensitivities of less than 50 mJ/cm2. The photopatterning process is believed to proceed by base-catalyzed reaction of resin-based silanol groups with neighboring silyl hydride groups to yield thermally stable siloxane crosslinks. Copyright

Integration of a low stress photopatternable silicone into a wafer level package

This paper describes a novel wafer level package using a silicone under the bump (SUB) design. The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the die and the printed circuit board (PCB). Integration of a low modulus silicone pad between the die and solder ball allows for additional deformation mechanisms to dissipate stress between the die and the PCB during thermal cycling, increasing device reliability. Key to the realization of a SUB device was the integration of an elastomeric pad using the recently commercialized Dow Corning/sup /spl reg// WL-5150 photodefinable spin-on silicone. SUB devices containing 40 /spl mu/m thick silicone pads were successfully built using a series of standard processing steps including photolithography, plasma cleaning, and metallization. Two different SUB solder joint designs, suggested by FEA, were constructed and evaluated under thermal cycling. Failure mechanisms in the devices were determined to be dependent on the metallization scheme for the electronic connections. Incorporation of the silicone pads in a SUB device resulted in a 90% increase in reliability relative to control devices without the silicone pad. The failure mechanisms observed suggested an intermediate metallization approach to further enhance reliability.

An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration

Silicone Under the Bump (SUB) is a novel wafer level packaging (WLP) concept aimed at improving the reliability of solder joints. Poor reliability of the solder joints is amibuted to large stresses generated by a mismatch between the thermal expansion coefficient of the chip and that of the printed circuit hoard. The severity of this problem increases with chip sue. The SUB is integrated into the package between the chip and solder joint. Improvement in the solder joint reliability on thermal cycling results tlom dissipation of the stresses into the low modulus silicone layer. Non-linear 3D Finite Element Analysis (EA) bas been used to predict the reliability of a model package under thermal cycling. The model incorporates a SUB design with the electrical interconnect layer partially covering the silicone. Simulation with a virtual design of experiment has been performed to assess the sensitivity of the models design parameters to the induced plastic strain in the solder and metallization. These parameters include the metal lead configuration, the geometry of the SUB and the material properties of the SUB. The time and an increase in the manufacturing cost [6]. As a lower cost process, WLPs have several advantages that will further grow as the sue of wafers continues to increase. However, to take advantage of the economy of the process, the solder joint reliability of WLPs needs to be improved. Such improvement is expected for a SUB based WLP design hut factors such as the SUB material properties and geomehy need to he defmed for optimum performance. It is anticipated that design optimization will provide sufficient performance to allow for wafer level packaging of memory chips in spite of their relatively large die size [7]. This paper presents an overview of simulation results pertaining to the thermo-mechanical behavior of a model WLP package with a SUB design. The fundamental damage mechanism associated with accumulated plastic strain in the solder and metallization are discussed in relation to the sensitivity factors that include, the metal lead width and position, the geometry of the SUB and material properties of the SUB. The thermomechanical results were used as a baseline for comparing the model trends. magnitude of the thermal cycling damage was represented by The technology nf SUEWLP package an increment of the equivalent plastic strain in each ~~il~~ analysis of relatively large silicon wp devices metallization layer and solder joint. The results suggest that mounted onto a PCB and to thermal cycles has Using a narrow metallization Ship on the SUB Significantly shown that the solder joint reliability is very low [SI. To rd~ces damage to the solder. However, fatigue damage to the reduce the damage caused by the accumulated inelastic strain metallization then hecomes the critical for in the solder, a flexible silicone hump is placed between the

Photopatternable silicone compositions for electronic packaging applications

Development of the next generation of electronics devices is creating a need for new specialized materials, application and integration processes for building reliable yet sophisticated packaging architectures. Key physical property attributes of these new materials include flexibility, low stress, and high thermal stability. To meet these needs Dow Corning is developing a family of spin coatable photopatternable silicone materials, application processes, as well as integration know-how to assist device manufactures in building the next generation of devices enabled by silicone based material technologies. These new materials can be easily coated onto electronics substrates and have been patterned using a commercially available stepper from Ultratech Inc. Films with a thickness ranging from 6 to 50 /spl mu/m have been demonstrated with patterned features resolved to 20 /spl mu/m dimensions in 20 /spl mu/m thick films. The etched regions provide a shallow sidewall slope and smooth curved surfaces that facilitate direct on silicone metallisation. After patterning the films can be cured at low temperatures (150 to 250/spl deg/C) to provide modulus values in the range of 150 to 500 MPa. These materials are inherently hydrophobic and are based on a cure System that is acid free and delivers highly thermally stable crosslinks without the need to outgas photocatalysts or ancillary chemicals. As a result, the films show very little shrinkage during thermal cure (/spl sim/2%), do not require extended high temperature processing, and provide a very low stress (<5 MPa). Yet in spite of their low temperature cure capability these materials show excellent thermal stability and mechanical integrity when exposed to high temperatures.

Introducing a silicone under the bump configuration for stress relief in a wafer level package

Microelectronics devices continue to evolve towards increased functionality, thinner die, increased reliability, and reduced cost, requiring a change in material and process requirements for the next generation of packages (i.e. stacked chip packages and wafer level packages (WLP)). Stress reduction is a key factor for many devices, particularly those that have thinner die and those that are subjected to stresses generated by thermal cycling. Wafer level packaging is an area where low stress and high volume manufacturing are critical for achieving good reliability and low manufacturing cost. Dow Coming and IMEC have been investigating a Silicone Under the Bump (SUB) wafer. level package as a potential route towards increased reliability. Including a SUB design into the device architecture provides a route to dissipate the stresses generated by the thermal expansion mismatch between the silicon die and the printed circuit board. Key to the device build is the application of a silicone pad using a photosensitive silicone or a screen printable silicone. In the design, metal traces from the bonding pads are redistributed to the tops of the silicone pads. Solder balls are placed on the metallized pads to complete the interconnection. The elastomeric nature of the pad dissipates the stresses created by the mismatch in CTE between the chip and the PCB and extends device reliability. To build the SUB enabled WLP device it was critical to understand the impact of the new materials on the device process steps. The uniqueness of the material set requires the creation and optimization of plasma cleaning processes specific to silicones, direct-on-silicone metallization and metal etching in the presence of silicones. The application of a solder mask and solder ball placement is required to complete a successful device build. In this paper we will discuss in detail the process steps utilized in building a silicone containing WLP. This will include a discussion on the process challenges including silicone pad integration, metallization, solder mask application and solder ball placement. The methodologies described in this paper can be generally applied for integration of photopatternable silicones into a range of devices and packages.

Study of low-modulus die attach adhesives and molding compounds on warpage and damage of PBGA

Numerical experiments based on the three-dimensional (3D) nonlinear finite element method (FEM) has been conducted to understand governing damage mechanisms during the die attachment for the ball grid array (BGA) packages. The parametric studies for various designs of the BGA package and material properties have been performed. A wide range of the modulus (1MPa~30GPa) and the coefficient of thermal expansion (CTE) (10ppm ~ 300ppm) were evaluated to see feasibility of a new class of material set in the die attach adhesive. Effects of thermo-mechanical properties, particularly glass transition temperature (Tg) of selected die attach adhesives on the damage and warpage of the die and substrate of BGA are analyzed. The warpage of substrate and Si die cracking due to the material properties of the die attach adhesive are demonstrated. Classification of modes of deformation in the BGA package with material sets will shed light on novel material development for better reliability. In addition, the optimum thermo-mechanical properties of die attachment materials and molding compounds will be selected based on the parametric studies