Herman Meynen

Properties of porous HSQ-based films capped by plasma enhanced chemical vapor deposition dielectric layers

This article presents a study on Dow Corning® XLK™, an inorganic porous material with about 50% porosity and a dielectric constant of 2.0. It focuses on matters linked to sealing the porous film by depositing a plasma enhanced chemical vapor deposition (PECVD) dielectric cap layer. The study shows that the material can be modified during cap deposition due to the fast diffusion of reactants and radicals through the porous network, and acquire totally new properties which can be either beneficial or detrimental, depending on the chosen process. In particular, it is found that cap deposition processes on XLK in an oxidizing ambient, as used for SiO2 deposition, should be avoided. On the other hand, a beneficial modification of the dielectric film has been observed after SiC:H capping. It is also shown that there exists a critical thickness of capping material below which the cap layer reveals the presence of pinholes. The critical thickness value for a PECVD SiC:H cap layer on top of an XLK film is around 2...

Process Optimization and Integration of Trimethylsilane-Deposited α-SiC:H and α-SiCO:H Dielectric Thin Films for Damascene Processing

The semiconductor grade organosilicon gas trimethylsilane (Dow Corning Z3MS) can be used to deposit unique amorphous hydrogenated silicon carbide (α-SiC:H)-based alloy films that exhibit desirable properties such as chemical resistance, low stress. low permittivity, and low leakage. These film characteristics are ideal for applications in Cu-damascene interconnect technology. In this work, the results of a comprehensive study of Z3MS plasma enhanced chemical vapor deposition (PECVD) dielectric films are reported where all depositions were performed in commercial production PECVD equipment. Processing for α-SiC:H films deposited from Z3MS/He mixtures was optimized for deposition rate, uniformity, and permittivity. The processing parameters can be tuned for relative permittivity down to κ ∼ 4.2 making α-SiC:H an attractive substitute for PECVD silicon oxide or silicon nitride. Using mixtures of Z3MS and N 2 O precursors, α-SiCO:H films were deposited with very high deposition rates and film permittivity as low as κ ∼ 2.5. These films have been applied in damascene technology. Physical properties and stability of blanket films were studied. Measurement of relative permittivity, leakage current, and breakdown voltage was performed on metal/dielectric/metal structures. Fourier transform infrared, X-ray photoelectron, and high-energy ion scattering spectrometry were used to determine bonding and film compositions. Integration issues related to deep ultraviolet lithography, dry etch, strip, and metallization are discussed. Optimized film processes were integrated into 0.18 μm Cu damascene interconnect process technology and the electrical results were compared to standard PECVD oxide. The results of these studies indicate that the device performance improvements inferred from the blanket film properties can be realized in fully integrated interconnect structures.

Integration of a low stress photopatternable silicone into a wafer level package

This paper describes a novel wafer level package using a silicone under the bump (SUB) design. The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the die and the printed circuit board (PCB). Integration of a low modulus silicone pad between the die and solder ball allows for additional deformation mechanisms to dissipate stress between the die and the PCB during thermal cycling, increasing device reliability. Key to the realization of a SUB device was the integration of an elastomeric pad using the recently commercialized Dow Corning/sup /spl reg// WL-5150 photodefinable spin-on silicone. SUB devices containing 40 /spl mu/m thick silicone pads were successfully built using a series of standard processing steps including photolithography, plasma cleaning, and metallization. Two different SUB solder joint designs, suggested by FEA, were constructed and evaluated under thermal cycling. Failure mechanisms in the devices were determined to be dependent on the metallization scheme for the electronic connections. Incorporation of the silicone pads in a SUB device resulted in a 90% increase in reliability relative to control devices without the silicone pad. The failure mechanisms observed suggested an intermediate metallization approach to further enhance reliability.

An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration

Silicone Under the Bump (SUB) is a novel wafer level packaging (WLP) concept aimed at improving the reliability of solder joints. Poor reliability of the solder joints is amibuted to large stresses generated by a mismatch between the thermal expansion coefficient of the chip and that of the printed circuit hoard. The severity of this problem increases with chip sue. The SUB is integrated into the package between the chip and solder joint. Improvement in the solder joint reliability on thermal cycling results tlom dissipation of the stresses into the low modulus silicone layer. Non-linear 3D Finite Element Analysis (EA) bas been used to predict the reliability of a model package under thermal cycling. The model incorporates a SUB design with the electrical interconnect layer partially covering the silicone. Simulation with a virtual design of experiment has been performed to assess the sensitivity of the models design parameters to the induced plastic strain in the solder and metallization. These parameters include the metal lead configuration, the geometry of the SUB and the material properties of the SUB. The time and an increase in the manufacturing cost [6]. As a lower cost process, WLPs have several advantages that will further grow as the sue of wafers continues to increase. However, to take advantage of the economy of the process, the solder joint reliability of WLPs needs to be improved. Such improvement is expected for a SUB based WLP design hut factors such as the SUB material properties and geomehy need to he defmed for optimum performance. It is anticipated that design optimization will provide sufficient performance to allow for wafer level packaging of memory chips in spite of their relatively large die size [7]. This paper presents an overview of simulation results pertaining to the thermo-mechanical behavior of a model WLP package with a SUB design. The fundamental damage mechanism associated with accumulated plastic strain in the solder and metallization are discussed in relation to the sensitivity factors that include, the metal lead width and position, the geometry of the SUB and material properties of the SUB. The thermomechanical results were used as a baseline for comparing the model trends. magnitude of the thermal cycling damage was represented by The technology nf SUEWLP package an increment of the equivalent plastic strain in each ~~il~~ analysis of relatively large silicon wp devices metallization layer and solder joint. The results suggest that mounted onto a PCB and to thermal cycles has Using a narrow metallization Ship on the SUB Significantly shown that the solder joint reliability is very low [SI. To rd~ces damage to the solder. However, fatigue damage to the reduce the damage caused by the accumulated inelastic strain metallization then hecomes the critical for in the solder, a flexible silicone hump is placed between the

Low cost, room temperature debondable spin-on temporary bonding solution: A key enabler for 2.5D/3D IC packaging

We report the development of a bi-layer spin on temporary bonding solution (TBS) which eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post treatment for debonding. Thus it greatly increases the throughput of the temporary bonding/debonding process. It also provides a total thickness variation (TTV) of less than 1 μm for spin coated films on both 200 mm and 300 mm wafers which enable the TTV of 300 mm bonded pairs to be 2-3 μm for bumped wafers using 70 and 100 μm thick adhesive films after backgrinding for an unoptimized bonding process. Furthermore, we have demonstrated the chemical and thermal stability of both the material and the bonded pair by exposing the bonded wafer pair to common chemicals (phosphoric acid, nitric acid, organic solvents etc.) and temperature conditions (up to 300 C) used in the TSV process. Additionally, the time taken for the entire spin coat-bond-debond process was less than 15 minutes with room for further improvement. Based on the current results, it is expected that the current bi-layer based temporary bonding solution has the potential to play an important role in enabling the high volume manufacturing of 2.5D/3D IC stacking.

Photopatternable silicone compositions for electronic packaging applications

Development of the next generation of electronics devices is creating a need for new specialized materials, application and integration processes for building reliable yet sophisticated packaging architectures. Key physical property attributes of these new materials include flexibility, low stress, and high thermal stability. To meet these needs Dow Corning is developing a family of spin coatable photopatternable silicone materials, application processes, as well as integration know-how to assist device manufactures in building the next generation of devices enabled by silicone based material technologies. These new materials can be easily coated onto electronics substrates and have been patterned using a commercially available stepper from Ultratech Inc. Films with a thickness ranging from 6 to 50 /spl mu/m have been demonstrated with patterned features resolved to 20 /spl mu/m dimensions in 20 /spl mu/m thick films. The etched regions provide a shallow sidewall slope and smooth curved surfaces that facilitate direct on silicone metallisation. After patterning the films can be cured at low temperatures (150 to 250/spl deg/C) to provide modulus values in the range of 150 to 500 MPa. These materials are inherently hydrophobic and are based on a cure System that is acid free and delivers highly thermally stable crosslinks without the need to outgas photocatalysts or ancillary chemicals. As a result, the films show very little shrinkage during thermal cure (/spl sim/2%), do not require extended high temperature processing, and provide a very low stress (<5 MPa). Yet in spite of their low temperature cure capability these materials show excellent thermal stability and mechanical integrity when exposed to high temperatures.

Introducing a silicone under the bump configuration for stress relief in a wafer level package

Microelectronics devices continue to evolve towards increased functionality, thinner die, increased reliability, and reduced cost, requiring a change in material and process requirements for the next generation of packages (i.e. stacked chip packages and wafer level packages (WLP)). Stress reduction is a key factor for many devices, particularly those that have thinner die and those that are subjected to stresses generated by thermal cycling. Wafer level packaging is an area where low stress and high volume manufacturing are critical for achieving good reliability and low manufacturing cost. Dow Coming and IMEC have been investigating a Silicone Under the Bump (SUB) wafer. level package as a potential route towards increased reliability. Including a SUB design into the device architecture provides a route to dissipate the stresses generated by the thermal expansion mismatch between the silicon die and the printed circuit board. Key to the device build is the application of a silicone pad using a photosensitive silicone or a screen printable silicone. In the design, metal traces from the bonding pads are redistributed to the tops of the silicone pads. Solder balls are placed on the metallized pads to complete the interconnection. The elastomeric nature of the pad dissipates the stresses created by the mismatch in CTE between the chip and the PCB and extends device reliability. To build the SUB enabled WLP device it was critical to understand the impact of the new materials on the device process steps. The uniqueness of the material set requires the creation and optimization of plasma cleaning processes specific to silicones, direct-on-silicone metallization and metal etching in the presence of silicones. The application of a solder mask and solder ball placement is required to complete a successful device build. In this paper we will discuss in detail the process steps utilized in building a silicone containing WLP. This will include a discussion on the process challenges including silicone pad integration, metallization, solder mask application and solder ball placement. The methodologies described in this paper can be generally applied for integration of photopatternable silicones into a range of devices and packages.

Optimization of etching and stripping chemistries for Z3MS/sup TM/ Low-k

Silicon-Oxy-Carbide (SiOC) materials are used as low-k materials for the 2.7-k generation. They can be etched with the fluorinated chemistries used for oxide but some optimizations are needed to achieve acceptable etch-rates and good selectivities. The resist strip is also very sensitive and requires even more development to keep the material properties intact after full damascene integration. Oxygen is useful but it can also cause severe damage. All experiments described in this paper were performed on Z3MS/sup TM/ Low-k(*).

Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films

Physical and electrical characterization of a Dow Corning silsesquioxane-based ultra-low k dielectric is presented. The film properties, such as refractive index, SiH bond density, thermal stability and susceptibility to moisture absorption are investigated as a function of processing conditions. It is shown that exposure of the films to plasma environments results in a change of porosity. A low-K dielectric film with a pore size around 3.5 nm is successfully integrated in 0.2 /spl mu/m single damascene structures.

Low-k materials etch and strip optimization for sub 0.25 /spl mu/m technology

With the introduction of low-k materials into the intermetal dielectric (IMD) layers, it is important to optimize the via etch process in order to minimize the IMD degradation that is caused by harsh O/sub 2/ and wet stripping treatments. A simple, sensitive, and cost-effective measurement method is introduced for the determination of low-k material degradation caused during the via etch process. By using a single damascene comb structure, a large sidewall area of low-k material can be exposed to the etch strip process in question. The intra-line capacitance between the trenches is an extremely sensitive parameter to evaluate material degradation. Using this method, etch and strip processes can be tailored for a specific low-k material, which in turn, improve the interconnect performance and via yield. The results from this method are identical to results coming from the optimization of electrical performance with completely integrated chips and is in very good agreement with FTIR analysis for bare films.