Brian Sapp

Metrology needs for through-silicon via fabrication

Abstract. This paper focuses on the metrology needs and challenges of through-silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper chemical mechanical planarization. These TSVs, with typical dimensions within a factor of two or so of ≈5  μm  ×50  μm (diameter×depth), present an innovative set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of L/B/S metal; metrology for these layers determines whether there is complete coverage of the sidewalls. Metrology for the fill step includes verifying that the TSVs are deposited without voids and that the extent of stress on the surrounding silicon does not exceed acceptable limits.

TSV and Cu-Cu direct bond wafer and package-level reliability

A comprehensive study of reliability failure modes in an advanced through-silicon via (TSV) mid process flow is presented in Part I of this paper. This is the first time unique TSV mid reliability failure modes at leading-edge TSV dimensions have been observed and reported. TSV Kelvin, comb and chain test structures with 10:1 aspect ratio and a TSV diameter of 5.5 μm are manufactured using a state-of-the-art TSV process. Through standard BEOL reliability testing and physical failure analysis, we observe that the dielectric and barrier layers close to the bottom of the TSV and the TSV redistribution layer (RDL) interface emerge as the main sources of failures. Voltage ramp dielectric breakdown (VRDB) is compared with time-dependent dielectric breakdown (TDDB) measurements. It is found that VRDB correlates well with TDDB and can serve as a fast method for evaluating process changes or as an in-line process monitor. Copper-to-copper direct bonding (CuDB) is the leading candidate for ultra-high density chip-to-chip interconnects in 3D stacked ICs, because it has the potential to match leading-edge TSV pitches. It is important to consider the reliability aspects of the combined TSV and CuDB interconnect system in a package context. Part II of this paper reports on the design of a TSV and CuDB chip-package interaction test vehicle and first reliability results of the TSV/CuDB combined interconnect.

Challenges in thin wafer handling and processing

Through-silicon via (TSV)-based 3D packaging technologies require processing and handling of silicon wafers thinned to 50 μm and below. A number of manufacturing challenges exist for these processes. When wafers are this thin, an external means of mechanical support is always required. This support may be provided from specially designed chucks, rigid carrier wafers, dicing tape or the final package. Using rigid carrier wafers and a temporary bonding process allows the thin wafers to be processed in regular semiconductor tooling. The number of processes available for temporary bonding as well as the variety of integration flows adds complication to process development in the area. Furthermore, these processing steps require some restructuring of the current semiconductor supply chain.

Thermo-mechanical and electrical characterization of through-silicon vias with a vapor deposited polyimide dielectric liner

A study using a vapor deposited polyimide (VDP) dielectric liner to electrically isolate through-silicon vias (TSVs) has demonstrated electrical and thermo-mechanical performance superior to sub-atmospheric chemically vapor deposited (SACVD) tetraethyl orthosilicate (TEOS) liner in 5 μm × 50 μm TSVs. The VDP liner is continuous and highly conformal, with a worst-case coverage of 85% relative to the target deposition thickness. Moreover, the material integrates through TSV metallization, anneal, and polish. Electrically, VDP provides lower inter-via capacitance than the more conventional SACVD TEOS liner. Mechanically, blanket film stress of VDP measured as a function of temperature shows no hysteresis up to 400°C and a stress delta during cycling of only 45 MPa. The delta is an order of magnitude lower than SACVD TEOS. The thermo-mechanical behavior of VDP also results in a lower residual stress in the silicon area surrounding the structure, which enables a smaller keep-away zone for TSVs and effectively increases the density of transistors in silicon for 3D integrated systems.

Direct copper electrodeposition on a chemical vapor-deposited ruthenium seed layer for through-silicon vias

Direct plating of Cu on Ru for dual damascene and high aspect ratio through-silicon via (TSV) structures requires high nucleation density and rapid coalescence of the Cu nuclei, which may be achieved by incorporating strong suppressors in the plating solution. Atotech Spherolyte plating chemistry, containing a unique strong suppressor, is able to generate a nucleation density greater than 1012 cm-2. No pretreatment of the Ru surface is necessary. Void-free, bottom-up fill has been repeatedly demonstrated within 40 min using this chemistry for 5 μm × 50 μm TSV structures without Cu seeds. Material characterizations including time-of-flight secondary ion mass spectrometry (ToF-SIMS) and electron backscatter diffraction (EBSD) analyses of the plated TSVs have been conducted and discussed.

Mechanism of low-temperature copper-to-copper direct bonding for 3D TSV package interconnection

Cu-Cu direct bonding is the leading method for fine pitch (10 μm) chip-to-chip interconnects. We performed several measurements on blanket Cu film samples in an effort to determine the impact of the Cu film properties on wafer-to-wafer Cu-Cu direct bonding. X-ray photoelectron spectroscopy (XPS) measurements were performed on uncleaned and cleaned samples to evaluate the effectiveness of three surface cleaning methods, Ar sputtering in vacuum, forming gas annealing and N2 annealing (NA). The XPS results were correlated with the bonding quality of the wafers cleaned by above mentioned methods using a C-mode scanning acoustic microscope (CSAM) and four-point bending test. The grain structure and texture information of the Cu surface were studied by scanning electron microscopy (SEM) and electron backscatter diffraction (EBSD) and the residual stress of Cu films was measured by X-ray diffraction (XRD). The roles that these microstructural variables may play in Cu-Cu direct bonding were also discussed.

Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

In this paper, physical and electrical results of full wafer direct Cu plating of 2×40 μm TSVs with thin Ru seed are presented. Physical vapor deposition of about 100 nm Cu in the field is shown to improve plating non-uniformity across the structured wafer. TSV plating using Atotechs TSV III chemistry results in bottom-up growth with strong TSV sidewall suppression and void free TSV fill. Early results for in-line electrical test and voltage ramp dielectric breakdown reliability testing are discussed.

300mm wafer level sulfur monolayer doping for III–V materials

We have demonstrated sulfur monolayer doping (MLD) of In(53%)GaAs on III-V buffer/Si substrate at 300mm wafer scale and obtained sheet resistance of 303 ohms/sq with 8% uniformity. Mono-layer doping was achieved via molecular doping of sulfur and conventional annealing for dopant drive-in. Chemical reactivity, cost, environmental, safety and health aspects (all of which are crucial for high volume manufacturing) were considered in the chemical down-selection. MLD demonstrates molecular-scale control with conformal, nondestructive introduction of dopants to III-V materials.

Post TSV etch cleaning process development using SAPS megasonic technology

In this paper, the method of space alternated phase shift (SAPS) megasonic technology is applied for post-etch (Bosch) TSV wafers cleaning process. The SAPS technology provides uniform sonic energy on each point of entire wafer by alternating phase of megasonic wave in the gap between a megasonic device and the wafer. For this study, 5×50 μm post-etch (Bosch) TSV wafers were used. Experimental verification is provided using both physical analysis and electrical test. SEM equipped with an EDX was used to detect the presence of fluoropolymer residue (i.e., CXFY) for pre- and post-cleaning TSV coupons, FIB-SEM was used to evaluate copper plating performance; TSV leakage current map and Voltage ramp dielectric breakdown (VRDB), which act as principal electrical reliability metric, were also used to assess cleans effectiveness. The test results indicate that the megasonic energy can propagate to the bottom of TSV, and the wafers undergo SAPS cleaning process exhibit obvious electrical performance enhancement comparing with those cleaned by conventional single-wafer spray approach.

Methodology to evaluate pre-applied underfill materials with concurrent flux capability for ultra-fine pitch solder-based interconnects

This work describes a methodology and a test structure to evaluate next generation pre-applied underfill materials with concurrent flux capability for ultra-fine pitch solder-based interconnects. This simple test vehicle consists of Sn-solder micro-bumps with diameters less than 10 μm. The micro-bumps reflowed to form spherical balls when heated in reducing environments. The micro-bumps are used to evaluate the concurrent flux capability of two pre-applied underfill materials. Thermosetting temperatures and viscous behavior of the pre-applied underfill materials were measured by differential scanning calorimetry (DSC) to understand the flow response of the Sn-solder micro-bumps. X-ray tomography was evaluated using this test vehicle as a technique for monitoring the bump interface through a full thickness Si wafer and underfill material.