Brian T. Vaccaro

Method for equivalent acceleration of JEDEC/IPC moisture sensitivity levels

This paper reports a new equivalent test procedure to accelerate JEDEC/IPC moisture sensitivity level testing for plastic surface mount packages. The methodology is developed from moisture diffusion analysis augmented by the use of the critical interface concentration dependency. Equivalent moisture ingress behaviour is shown to be obtainable for any combination of mould compound type and package thickness. The new test procedure, based on testing at 60/spl deg/C/60% RH, reduces the total required moisture soak time for Levels 3-5 by approximately a factor of five compared to the times required for 30/spl deg/C/60% RH testing. An additional benefit of the accelerated test procedure is the introduction of a new moisture level defined as a one month floor life at ambient exposure conditions of 30/spl deg/C/60% RH or less. The required soak time to perform this new moisture level is only 120 hours. Equivalency of the new accelerated test conditions is proven by moisture/reflow experiments on a variety of package types ranging from thin QFPs (TQFPs) and PLCCs to plastic ball grid arrays (PBGAs). Damage response, assessed from inspection for internal cracking and delamination using acoustic microscopy, indicates that the new test procedures are well correlated and considered indistinguishable in most cases.

Lead free packaging and Sn-whiskers

Replacement of Pb/Sn terminations on electronic devices with pure Sn has proven to be much more difficult than expected. The main problem is Sn whisker formation. Sn whiskers are single crystal, mechanically strong, metallic filaments that can nucleate and grow over time in such a way as to lead to device failure in the field. In this study, we present the results of Sn-whisker formation and growth studies for plated matte-Sn on copper lead frames employing stress tests as outlined in the proposed JEDEC Sn-whisker specification. The results indicate that the propensity for whisker formation decreases with increasing Sn-thickness, and with a post plate heat treatment. The propensity for whisker growth is found to dramatically change once the devices are subjected to a melting of the matte-Sn plating. A reflow preconditioning is found to be a major variable influencing the formation and growth of Sn-whiskers on bare Cu lead frames which even negates the potential benefits for thicker Sn-plates and a post-plate anneal. Only the application of a Ni-underplate was found to produce a truly robust matte-Sn whisker solution resistant to excessive whisker growth in both the as-made and post-reflowed states.

Moisture blocking planes and their effect on reflow performance in achieving reliable Pb-free assembly capability for PBGAs

Moisture/reflow testing on plastic ball grid array (PBGA) packages for Pb-free assembly applications has revealed a potential performance issue associated with moisture diffusion within the organic layers of PBGA substrates. Diffusion of moisture within the composite organic layers of the substrate is found to be effectively blocked by the presence of large metal power and ground planes. For short ambient exposure times, these planes impede the ingress of moisture and limit initial moisture uptake. However, when dry baking becomes necessary after extended periods of exposure to ambient conditions, the metal planes are then found to hinder the egress of moisture, thereby forcing significantly longer bake times. This paper addresses the critical nature of moisture interaction within the inner-organic layers of PBGA substrates and demonstrates the potential concerns for long-term handling effects. Residual moisture contained within the organic layers is found to play an important role for moisture/reflow performance at the higher Pb-free assembly temperatures. Finite element analysis (FEA) is used to detail the moisture diffusion process within the internal package features for PBGAs. Key material property data are measured and presented. Important aspects of fast diffusion paths associated with glass fiber reinforced substrates are also accounted for. Finally, experimental moisture/reflow data collected on 2 and 4-layer PBGAs are presented.

Large die flip chip packaging on organic substrates. the role of finite element analysis (FEA), materials characterization, failure analysis (FA) and test vehicles in development spins

This work describes a case study where a process was developed focusing on four key factors that can be used to defme a methodology for packaging large die on high performance organic substrates: failure analysis (FA), f~te element analysis (FEA), test vehicle development and materials testing. The process consisted of in depth FA in the prototype phase to identify failure modes within typical thermomechanical stress tests such as air - to -air thermal cycling. Armed with a known failure mode, we desaihe the efforts to characterize a variety of assembly materials and utilize 3-D FEA of stress and warpage to determine optimal package construction. The use of low cost, quick turn test vehicles allowed us to verify the predicted optimal package and materials combinations through simple opens / shorts electrical tests during JEDEC reliability testing. Processability evaluations and optical coplanarity measurements allowed us to quickly select materials based on minimized warpage and optimum underfill characteristics. The result of this effort is a systematic approach to identify reliable large die flip chip packaging options for organic substrates in a cost effective, timely manner. 1. Iutrnductinn The use of failure analysis, materials testing, test vehicle development, and fmite element analysis (FEA) has been sbown to be indispensable at arriving at reliable packaging solutions. [l-31 Many researchers have used FEA as an important tool to evaluate package stresses and in some cases identify potential reliability limiting artifacts [4]. However, failure mode analysis is clearly the mnst important link to the usefulness of FEA as a tool for the packaging engineer. FEA alone cannot necessarily identify intrinsic weaknesses in a package design. Flip chip assemblies are complex systems containing elaborate geometries and material combinations. Beyond the obvious path of reducing the overall stress at interfaces and at other critical regions in a package, it is very difficult to identify the intrinsic weakness within the assembly until a failure occurs and methodical failure analysis identifies the root cause. Clearly, the need for inexpensive, readily available test assemblies to “mine sweep” potential failure modes in the presence of accelerated test conditions is required to perform product development at an acceptable pace, while keeping costs under control. FEA results will only be as good as the material property data provided. Due to the variety of measurement techniques and relative capabilities of materials vendors, the required material property data can he dfiicult to interpret correctly We present a case study where a failure mode was identified for a particular die size / body size combmation to enable a portion of OUT flip chip package portfolio. In order to accommodate the introduction of large SoC and high functionality die, the need to develop a packaging solution that extended this portfolio within the same substrate technology (as well as others) became apparent. The process by which this extension was made possible consisted of a systematic, four part knowledge based scheme using the tools mentioned above. We performed careful analysis of the existing failures followed by standardized materials characterization to enable the in depth FEA modeling required to understand the nature of the failure and to enable the extension of our package technology for large silicon. The use of carefully designed and inexpensive test vehicles, to perform evaluations at qualification stress conditions, allowed us to verify our model and to prove in an assembly process just ahead of product introduction.