Brian W. Kernighan

A Procedure for Placement of Standard-Cell VLSI Circuits

This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

Software tools

Building on the work of others is the only way to make substantial progress in any field. Yet computer programming continues as a cottage industry because programmers insist on reinventing programs for each new application, instead of using what already exists. We must encourage a way of packaging programs so that they can be perceived as standard tools, each performing its specialized task sufficiently well and interfacing to other tools so conveniently that programmers seldom feel any need to make their own version from scratch.In this paper we show how programmers can view substantial parts of what they do as tool building and tool using. By studying some specific examples of general purpose tools, we show how programs can be packaged as tools, so other programmers will use them in preference to building their own. We also comment on the sort of programming environment which seems most hospitable to the development and use of tools.

WISE design of indoor wireless systems: practical computation and optimization

Designing a low-power system for wireless communication within a building might seem simple. Not so-walls can affect signal strength in ways that are hard to calculate. The paper considers how AT&Ts WISE software uses CAD, computational geometry, and optimization to quickly plan where to place base-station transceivers. >

A proper model for the partitioning of electrical circuits

Partitioning algorithms for electrical circuits are often based on the heuristic manipulation of a simple element-to-element interconnection matrix. However, the element-to-element interconnection matrix does not properly represent an electrical interconnection, or “net”, among more than two elements. This paper expands on several aspects of the discrepancy: 1) its source, 2) the circumstances under which it is likely to be significant, and its magnitude for typical circuits, and 3) the comparative difficulty and expense of using a more appropriate representation. A physically correct “net-cut” model is presented. This model is computationally straightforward and is easily adapted to the typical heuristic solution strategies. The “net-cut” model is coupled with the Kernighan-Lin partitioning algorithm [3]; using the same algorithm, comparisons with the “edge-cut” model demonstrate that the correct model reduces net-cuts by 19 to 50% for four digital logic circuits.

Awk — a pattern scanning and processing language

This paper describes the design and implementation of awk, a programming language which searches a set of files for patterns, and performs specified actions upon records or fields of records which match the patterns. Awk makes common data selection and transformation operations easy to express; for example, \documentclass{article}\pagestyle{empty}\begin{document}

An optimum channel-routing algorithm for polycell layouts of integrated circuits

{\rm length > 72}

PIC — A language for typesetting graphics

\end{document} is a complete awk program that prints all input lines whose length exceeds 72 characters. The program \documentclass{article}\pagestyle{empty}\begin{document}