Alfred E. Dunlop

TILOS: A Posynomial Programming Approach to Transistor Sizing

A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.

A Procedure for Placement of Standard-Cell VLSI Circuits

This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

Chip Layout Optimization Using Critical Path Weighting

A chip layout procedure for optimizing the performance of critical timing paths in a synchronous digital circuit is presented. The procedure uses the path analysis data produced by a static timing analysis program to generate weights for critical nets on clock and data paths. These weights are then used to bias automatic placement and routing in the layout program. This approach is shown to bring the performance of the chip significantly closer to that of an ideal layout which is assumed to have no delay due to routing between cells.

High-speed, burst-mode, packet-capable optical receiver and instantaneous clock recovery for optical bus operation

This paper describes an enhanced performance version of a high-speed burst-mode compatible optical receiver and its application to 622-Mb/s optical bus operation in conjunction with an instantaneous clock recovery scheme. The receiver is fabricated in a 12 GHz f/sub t/ silicon bipolar technology and consists of a differential transimpedance amplifier with an auto-threshold level controller and a high-speed quantizer. Using an InGaAs avalanche photodiode, the typical burst mode sensitivity is around /spl minus/34 dBm (10/sup /spl minus/9/ BER) at bit rates up to 1.5 Gb/s with a dynamic range of 26 db for both pseudorandom and burst signals. The results using a laser beam modulated by a high-speed external modulator indicate that the receiver can be operated at bit rates higher than 2 Gb/s. With a worst-case self-resetting time >

SLIM--The Translation of Symbolic Layouts into Mask Data

A new form of symbolic layout for integrated circuits is coupled with a mask compaction procedure which removes excess space while guaranteeing that all design rules are met. Tradeoffs between X and Y compaction are made based on critical path information. Two types of compaction are used to minimize mask area and computer run-time. Additional procedures reduce mask area by inserting jogs at strategic locations in the layout. A partitioned data base is used to store mask data in a hierarchical manner. The symbolic layout and mask compaction procedures require only 30 to 50 percent of the time traditionally needed to do equivalent hand layouts.

SLIP: symbolic layout of integrated circuits with compaction

Abstract SLIP (symbolic layout interpreted for polycells) is a program which uses symbolic layout information to generate NMOS polycells (standard cells) for small-scale and medium-scale integrated circuits. At the input level, the designer works with symbolic nodes and lines representing transistors, loads, interlayer contacts and connections. The relative locations of the nodes and lines are then used to generate a hard-coordinate mask description. The mask description is generated by first translating the relative location information of the symbolic layout into an initial legal mask layout. The mask layout is then compacted using a shear-line compaction technique. The program is written in the C programming language and is currentky running on a Hewlett-Packard 21 MX minicomputer.

Experiments using automatic physical design techniques for optimizing circuit performance

A system that accepts a transistor level net list, tunes it for high performance, and automatically lays it out is described. The system consists primarily of two components, TILOS and SC2D. The first component, TILOS, adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures are described, and their effect is illustrated with several examples, ranging from a few dozens of transistors to tens of thousands.<<ETX>>

150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection

Two 0.9 /spl mu/m CMOS chips serve for burst-mode clock and data recovery applications specific to passive optical network (PON) systems. In each case, a core, first order clock recovery circuit is realized by two gated ring oscillators, indirectly frequency-tuned by a phase-locked loop using a third replica oscillator and a local reference signal. Instantaneous phase locking is guaranteed by restarting the gated oscillators every time input data transitions occur. This method has been demonstrated to be precise enough to handle input data patterns containing hundreds of bits between transitions without errors. In addition, the circuit is small and dissipates low power. However, the recovered clock signal thus obtained inherits all jitter present in the input data signal. This shortcoming has been overcome in the present designs by two different methods. The results are the total elimination of jitter propagation and the generation of clean data and clock output signals. The first chip operates at 150 Mb/s. Since the data is demultiplexed into 8 channels, the local reference signal runs eight times slower than the transmission rate. This allows ample time for jitter-rejection processing. The second chip operates at 30 Mb/s without a demultiplexer. The jitter rejection is accomplished with an elastic store based on five 1 b registers.

A 9 Gbit/s bandwidth multiplexer/demultiplexer CMOS chip

A 622-MHz 28:7 multiplexer/demultiplexer (MUX/DEMUX) 0.9- mu m CMOS chip has been fabricated and tested. All inputs/outputs (I/O) communicate using 100 K ECL logic levels and are single-ended. The chip is packaged in a metal QFP (quad flat pack) package and generates less than 80 mV of ground noise when all outputs switch simultaneously. The total power dissipation is 2.5 W. The device has controlled loop-back paths for system diagnostic purposes. Tests show that the chip operates at more than 740 MHz.<<ETX>>

A set of switch-level synthesis tools

A set of switch-level synthesis tools is described. First, a tool, called sea-of-devices (SOD), that accepts an arbitrary transistor-level schematic and produces a gate-matrix style layout on a virtual grid is presented. The output is run through a compactor that does technology binding (MACS). Because it is a true cell compiler, SOD does not make use of any library of predefined cells: each subcircuit is laid out from scratch each time the tool is run. This means that the system can accept any circuit, including ones with individually sized transistors, such as those produced by the TILOS transistor sizer. Typical runs of SOD are in the 50-5000 transistor range. A tool which provides an efficient way to specify transistor circuits not limited to libraries, called the Switch-Level IC Compiler (SLICC), is discussed. It translates a subset of C directly into transistors, again without using any library, SLIC understands local logic transformations and CMOS rules (e.g. complementary and pass logic). It is not a general logic optimizer, but can accept the output of such a tool. The pipeline of a design is followed through SLICC, TILOS, SOD, and MACS.<<ETX>>