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Dive into the research topics where Hung Q. Le is active.

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Featured researches published by Hung Q. Le.


international solid-state circuits conference | 2007

Design of the Power6 Microprocessor

Joshua Friedrich; Bradley McCredie; Norman K. James; Bill Huott; Brian W. Curran; Eric Fluhr; Gaurav Mittal; Eddie K. Chan; Yuen H. Chan; Donald W. Plass; Sam Gat-Shang Chu; Hung Q. Le; Leo James Clark; John R. Ripley; Scott A. Taylor; Jack DiLullo; Mary Yvonne Lanzerotti

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.


international conference on ic design and technology | 2014

The POWER8 TM processor: Designed for big data, analytics, and cloud environments

Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuechli; Balaram Sinharoy; Eric Fluhr; Daniel M. Dreps; Victor Zyuban; Gregory Scott Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; Ryan Nett; Ruchir Puri; Phillip J. Restle; David Shan; Zeynep Toprak Deniz; Dieter Wendel; Matthew M. Ziegler; Dave Victor

POWER8™ delivers a data-optimized design suited for analytics, cognitive workloads, and todays exploding data sizes. The design point results in a 2.5x performance gain over its predecessor, POWER7+™, for many workloads. In addition, POWER8 delivers the efficiency demanded by cloud computing models and also represents a first step toward creating an open ecosystem for server innovation.


Archive | 2005

Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches

Pradip Bose; Alper Buyuktosunoglu; Richard James Eickemeyer; Lee Evan Eisen; Philip G. Emma; John Barry Griswell; Zhigang Hu; Hung Q. Le; D. Logan; Balaram Sinharoy


Archive | 2007

Universal Register Rename Mechanism for Targets of Different Instruction Types in a Microprocessor

Hung Q. Le; Dung Q. Nguyen; Balaram Sinharoy


Archive | 2012

Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions

Christopher Barton; Harold W. Cain; Bradly G. Frey; Hung Q. Le; Maged M. Michael; Raul Esteban Silvera; Derek Edward Williams; Michael Wong; Peng Wu


Archive | 2010

Hardware Assist Thread for Increasing Code Parallelism

Ronald Hall; Hung Q. Le; Raul Esteban Silvera; Balaram Sinharoy


Archive | 2014

INDEPENDENT MAPPING OF THREADS

Sam Gat-Shang Chu; Hung Q. Le; Jentje Leenstra; José E. Moreira; Dung Q. Nguyen; Brian W. Thompto


Archive | 2017

OPERATION OF A MULTI-SLICE PROCESSOR WITH AN EXPANDED MERGE FETCHING QUEUE

Kimberly Marie Fernsler; David A. Hrusecky; Hung Q. Le; Elizabeth A. McGlone; Brian W. Thompto


Archive | 2007

Universal Register Rename Mechanism for Instructions with Multiple Targets in a Microprocessor

Hung Q. Le; Dung Q. Nguyen; Balaram Sinharoy


Archive | 2018

ADMINISTERING INSTRUCTION TAGS IN A COMPUTER PROCESSOR

Kurt Alan Feiste; Hung Q. Le; David S. Levitan; Albert James Van Norstrand

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