Brice Rogie

State of the art of thermal characterization of electronic components using computational fluid dynamic tools

Purpose Latest Computational Fluid Dynamics (CFDs) tools allow modeling more finely the conjugate thermo-fluidic behavior of a single electronic component mounted on a Printed Wiring Board (PWB). A realistic three-dimensional representation of a large set of electric copper traces of its composite structure is henceforth achievable. The purpose of this study is to confront the predictions of the fully detailed numerical model of an electronic board to a set of experiment results to assess their relevance. Design/methodology/approach The present study focuses on the case of a Ball Grid Array (BGA) package of 208 solder balls that connect the component electronic chip to the Printed Wiring Board. Its complete geometrical definition has to be coupled with a realistic board layers layout and a fine description of their numerous copper traces to appropriately predict the way the heat is spread throughout that multi-layer composite structure. The numerical model computations were conducted on four CFD software then compare to experiment results. The component thermal metrics for single-chip packages are based on the standard promoted by the Joint Electron Device Engineering Council (JEDEC), named JESD-51. The agreement of the numerical predictions and measurements has been done for free and forced convection. Findings The present work shows that the numerical model error is lower than 2 per cent for various convective boundary conditions. Moreover, the establishment of realistic numerical models of electronic components permits to properly apprehend multi-physics design issues, such as joule heating effect in copper traces. Moreover, the practical modeling assumptions, such as effective thermal conductivity calculation, used since decades, for characterizing the thermal performances of an electronic component were tested and appeared to be tricky. A new approach based on an effective thermal conductivity matrix is investigated to reduce computation time. The obtained numerical results highlight a good agreement with experimental data. Research limitations/implications The study highlights that the board three-dimensional modeling is mandatory to properly match the set of experiment results. The conventional approach based on a single homogenous layer using effective thermal conductivity calculation has to be banned. Practical implications The thermal design of complex electronic components is henceforth under increasing control. For instance, the impact of gold wire-bonds can now be investigated. The three-dimensional geometry of sophisticated packages, such as in BGA family, can be imported with all its internal details as well as those of its associated test board to build a realistic numerical model. The establishment of behavioral models such as DELPHI Compact Thermal Models can be performed on a consistent three-dimensional representation with the aim to minimize computation time. Originality/value The study highlights that multi-layer copper trace plane discretization could be used to strongly reduce computation time while conserving a high accuracy level.

Practical steady-state temperature prediction of active embedded chips into high density electronic board

Printed Wiring Board die embedding technology is an innovative packaging alternative to address a very high degree of integration by stacking multiple core layers housing active chips. Nevertheless this increases the thermal management challenges by concentrating heat dissipation at the heart of the substrate and exacerbates the need of adequate cooling. In order to allow the electronic designers to early analyse the limits of the in-layer power dissipation, depending on the chip location inside the board, various analytical thermal modelling approaches were investigated. Therefore the buried active chips can be represented using surface or volumetric heating sources according with the expected accuracy. Moreover the current work describes the comparison of the volumetric heating source analytical model with the state-of-art numerical detailed models of several embedded chips configurations, and debates about the need or not to simulate in full details the embedded chips as well as the surrounding layers and micro-via structures of the substrate. The results highlight that the thermal behaviour predictions of the analytical model are found to be within ±5% of relative error and so demonstrate their relevance to model an embedded chip and its neighbouring heating chips or components. Further this predictive model proves to be in good agreement with an experimental characterization performed on a thermal test vehicle. To summarize, the developed analytical approach promotes several practical solutions to achieve a more efficient design and to early identify the potential issues of board cooling.

Experimental characterization of the predictive thermal behaviour model of a surface-mounted soft magnetic composite inductor

Abstract The latest low-profile high-power inductors, used in DC-DC converters to power an assortment of applications, are going endlessly smaller and submitted to larger amount of current. This surface-mounted magnetic component is commonly constructed using a wound copper coil which is over-moulded in a Soft Magnetic Composite (SMC) based on an iron-resin material mixture. The performances of that high-power density device depend closely on the coupled interaction of magnetic phenomenon, joule effect and thermal behaviour, which is difficult to apprehend at board level simulation. Thus, the present study highlights the electromagnetic phenomena encountered by SMC inductor devices and their influence on the temperatures of the iron-based core and copper-based coil. In order to better characterize the behaviour of high-power inductor devices, a set of coupled electromagnetic and thermal simulations were performed on the case of an industrial demonstration electronic board. Consequently, the influence of surrounding active electronic components upon the acceptable temperature rise of the inductor parts has been investigated. The numerical simulations were completed by electrical characterizations and thermal measurements on the test vehicle for various operating conditions with the purpose to establish a more realistic thermal model of the inductor device. The agreement of the fine detailed model with experiment results is quite relevant: the divergence is lower than 10%. Further, for minimizing the expensive meshing of the finely detailed simulations and the computation time, a novel concept of compact thermal model for inductor device, based on DELPHI methodology, was used. The deducted two-heating-source DELPHI-style model adequately correlates the physical behaviour of all heat paths of the inductor device, our purpose.

Evolution of the DELPHI compact thermal modelling method: An investigation on the boundary conditions scenarios

Board-level simulation has to consider, at the earliest stage of the conception, the impact of the vicinity of numerous high and medium powered devices. In 1996, the concept of Compact Thermal Model was defined, by the European consortium DELPHI to minimize the computation times, from days to minutes. A CTM resumes an electronic component as a simple cuboid form and a network of resistors that links a single temperature-sensitive node to major surfaces of heat extraction. Unfortunately the DELPHI method is restricted to steady-state model for mono-chip component. More complex issues such as multi-chip module or transient thermal model remain today for worldwide companies a non-trivial challenge. Our latest improvements made to generate steady-state multi-source CTM for System-In-Package devices showed that the number of boundary-condition scenarios is quite prohibitive when several nodes need to be monitored. The present work investigates the use of fractional factorial experiment, such as N-variables Doehlert design. The objective of this study is to define the lowest number of numerical simulations while keeping the highest accuracy level of the derived Boundary-Condition-Independent thermal network.