Eric Monier-Vinard

Delphi style compact modeling for multi-chip package including its bottom board area based on genetic algorithm optimization

Emerging packages offer diverse options for mounting active and passive devices in a single package, such as side by side, embedded or stacked die placements.

Delphi style compact modeling by means of genetic algorithms of system in Package devices using composite sub-compact thermal models dedicated to model order reduction

Nowadays a high-level integration with unprecedented functionality and efficient performances is achieved through 3D packaging techniques known as System-In-Package (SIP). The paper describes the reduction process conducted on a realistic SIP module case in order to establish a behavioral thermal network having a large number of power sources. Besides this device has been slightly modified to focus on the recent 3D integration techniques such as the stacking of chip, multi-chips side by side architecture or the embedding of conventional individually-packaged Integrated Circuits (IC). These works compared the prediction of a DELPHI style Compact Thermal Model (CTM) to a numerical Detailed Thermal Model with for aim to illustrate the diminution of computation delays, the expected accuracy and some efficient ways to improve it. Then it describes the performance of a novel methodology that nests a set of Sub-Compact Thermal Models (SCTM) within the detailed numerical model, far less grid-intensive, and its ability to preserve the final SIP CTM quality.

Thermal modelling of the emerging multi-chip packages

The thermal dissipation challenges that are seen today with single-chip components will only be magnified with the introduction of System in Package devices.

Electronic board modeling by the means of DELPHI compact thermal model of components

Board-level simulation considers the challenging process of analysing the impact of the vicinity of high and medium powered devices on the sensitive ones. This level of design is often considered in the industry sector as an unnecessary luxury. This damaging approach is becoming untenable with the rising use of miniaturized high-powered devices and High density Interconnection electronic board, which intensifies the coupling effect of neighbouring components. So, perform board-level thermal simulation at the earliest stage of the design process makes sense today, more than ever. To minimize the computation times, from days to minutes, the concept of compact thermal model was defined in 1996, by the European consortium DELPHI1 Unfortunately, DELPHI project ended with a methodology restricted to steady-state compact thermal model for mono-chip electronic component. Emerging problematic such as multi-chips module or transient thermal model were not addressed, which remains today for worldwide companies a non-trivial challenge. Since 2009, Thales is implementing these missing methods. The present paper summarizes the comparison of a “state-of-the-art” numerical detailed model and its deducted compact model with the help of infrared experimental results in order to promote a modelling guideline. (1)DEvelopment of Library of Physical model for an Integrated design environment.

Investigation of Delphi compact thermal model style for modeling surface-mounted Soft Magnetic Composite inductor

Recent works on System-In-Package component pointed out that its in-package inductor is the hottest part. It occurs that thermal stresses due to joule heating and magnetic losses can be damaging. The present study focuses on low profile, surface-mounted, Soft Magnetic Composite inductors to define their thermal behaviour and then to propose a guideline to create pertinent models.Results highlight the impact of thermal conductivity of composite core on temperatures and the lack of properties data of iron-resin mixtures. Using mixture model, a calculation of effective thermal conductivity is proposed.To minimize the expensive meshing of the fine detailed simulations and the computation time, a novel Compact Thermal Model for inductor, based on DELPHI methodology, was established. The predictions of CTM model show good agreement, less than 10% of divergence. Further works must be done to really master the coupled interaction of magnetic, joule effect, thermal phenomenon as well as material properties.

Dynamic Compact Thermal Model for stacked-die components

The present work proposes an approach to generate Dynamic Compact Thermal Models or “DCTMs” dedicated to electronic components. This one is based on the European project DELPHI, which defined the first comprehensive methodology concerning the generation of thermal behavioral model, Boundary Condition Independent, called Compact Thermal Models or “CTMs”. Unfortunately, the scope of “CTMs” was limited to the steady state as well as for single chip packages. But, the latest trend toward higher and higher density packaging using several chips requires henceforth a methodology capable to take into account the transient regime for 3D integration technologies like stacked-die solution. Following the CTMs modus operandi the DCTMs were conceived to propose a RC network able to predict a set of sensitive component temperatures with a minimized difference during component duty cycle. This work suggests the use of the genetic algorithms fitting technique that turns out relevant for the realization of DCTM, as well as the conventional DELPHI CTM.

Experimental characterization of DELPHI Compact Thermal Model for surface-mounted soft magnetic composite inductor

The latest low-profile high-power inductors, used in DC-DC converter to power an assortment of applications, are going endlessly smaller and submitted to larger amount of current. This surface-mounted magnetic component is commonly constructed using a wound copper coil which is over-moulded in a Soft Magnetic Composite (SMC) based on an iron-resin material mixture. The performances of that high-power density device are closely depending on the coupled interaction of magnetic phenomenon, joule effect and thermal behaviour, which are difficult to apprehend at board level simulation. In order to better characterize the behaviour of high-power inductor devices, a set of coupled electromagnetic and thermal simulations were performed on the case of an industrial demonstration electronic board. Further, the influence of surrounding active electronic components upon the acceptable temperature rise of the inductor parts has been investigated. The numerical simulations were completed by electrical characterizations and thermal measurements of the test vehicle for various operating conditions with the purpose to establish a more realistic thermal model of the inductor device. The agreement of the fine detailed model with experiment results is quite relevant: the divergence is lower than 10%. Moreover, the present study highlights the electromagnetic phenomena encountered by SMC inductor devices and their influence on the temperatures of the iron-based core and copper-based coil. This analysis confirms the conservative assumption that the magnetic and electrical losses can be uniformly applied to the core and coil volumes. The approach proposed in 2013, for the generation of a relevant Compact Thermal Model dedicated to SMC inductor devices, according with DELPHI methodology, remains valid.

Calculation limits of the homogeneous effective thermal conductivity approach in modeling of printed circuit board

Electronic components are continuously getting smaller. They embed more and more powered functions which exacerbate the temperature rise in component/board interconnect areas. Their design optimization is henceforth mandatory to control the temperature excess and to preserve component reliability. To allow the electronic designer to early analyze the limits of their power dissipation, an analytical model of a multi-layered electronic board was established with the purpose to assess the validity of conventional board modeling approaches. For decades, a vast majority of authors have been promoting a homogenous single layer model that lumped the layers of the board using effective orthotropic thermal properties. The work presents the thermal behavior comparison between a detailed multi-layer representation and its deducted equivalent lumped model for an extensive set of variable parameters, such as effective thermal conductivities calculation models or source size. The results highlight the fact that the conventional practices for Printed Circuit Board modeling can dramatically underestimate source temperatures when their size is very small.

State of the art of thermal characterization of electronic components using computational fluid dynamic tools

Purpose Latest Computational Fluid Dynamics (CFDs) tools allow modeling more finely the conjugate thermo-fluidic behavior of a single electronic component mounted on a Printed Wiring Board (PWB). A realistic three-dimensional representation of a large set of electric copper traces of its composite structure is henceforth achievable. The purpose of this study is to confront the predictions of the fully detailed numerical model of an electronic board to a set of experiment results to assess their relevance. Design/methodology/approach The present study focuses on the case of a Ball Grid Array (BGA) package of 208 solder balls that connect the component electronic chip to the Printed Wiring Board. Its complete geometrical definition has to be coupled with a realistic board layers layout and a fine description of their numerous copper traces to appropriately predict the way the heat is spread throughout that multi-layer composite structure. The numerical model computations were conducted on four CFD software then compare to experiment results. The component thermal metrics for single-chip packages are based on the standard promoted by the Joint Electron Device Engineering Council (JEDEC), named JESD-51. The agreement of the numerical predictions and measurements has been done for free and forced convection. Findings The present work shows that the numerical model error is lower than 2 per cent for various convective boundary conditions. Moreover, the establishment of realistic numerical models of electronic components permits to properly apprehend multi-physics design issues, such as joule heating effect in copper traces. Moreover, the practical modeling assumptions, such as effective thermal conductivity calculation, used since decades, for characterizing the thermal performances of an electronic component were tested and appeared to be tricky. A new approach based on an effective thermal conductivity matrix is investigated to reduce computation time. The obtained numerical results highlight a good agreement with experimental data. Research limitations/implications The study highlights that the board three-dimensional modeling is mandatory to properly match the set of experiment results. The conventional approach based on a single homogenous layer using effective thermal conductivity calculation has to be banned. Practical implications The thermal design of complex electronic components is henceforth under increasing control. For instance, the impact of gold wire-bonds can now be investigated. The three-dimensional geometry of sophisticated packages, such as in BGA family, can be imported with all its internal details as well as those of its associated test board to build a realistic numerical model. The establishment of behavioral models such as DELPHI Compact Thermal Models can be performed on a consistent three-dimensional representation with the aim to minimize computation time. Originality/value The study highlights that multi-layer copper trace plane discretization could be used to strongly reduce computation time while conserving a high accuracy level.

Practical steady-state temperature prediction of active embedded chips into high density electronic board

Printed Wiring Board die embedding technology is an innovative packaging alternative to address a very high degree of integration by stacking multiple core layers housing active chips. Nevertheless this increases the thermal management challenges by concentrating heat dissipation at the heart of the substrate and exacerbates the need of adequate cooling. In order to allow the electronic designers to early analyse the limits of the in-layer power dissipation, depending on the chip location inside the board, various analytical thermal modelling approaches were investigated. Therefore the buried active chips can be represented using surface or volumetric heating sources according with the expected accuracy. Moreover the current work describes the comparison of the volumetric heating source analytical model with the state-of-art numerical detailed models of several embedded chips configurations, and debates about the need or not to simulate in full details the embedded chips as well as the surrounding layers and micro-via structures of the substrate. The results highlight that the thermal behaviour predictions of the analytical model are found to be within ±5% of relative error and so demonstrate their relevance to model an embedded chip and its neighbouring heating chips or components. Further this predictive model proves to be in good agreement with an experimental characterization performed on a thermal test vehicle. To summarize, the developed analytical approach promotes several practical solutions to achieve a more efficient design and to early identify the potential issues of board cooling.